System on integrated chips and methods of forming same

Patent metadata

Field	Value
Publication number	US-9524959-B1
Application number	US-201514960225-A
Country	US
Kind code	B1
Filing date	Dec 4, 2015
Priority date	Nov 4, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

First claim

What is claimed is:

1. A method for forming a semiconductor package comprising:
attaching a first die to a first carrier;
depositing a first isolation material around the first die;
after depositing the first isolation material, bonding a second die to the first die, wherein bonding the second die to the first die comprises forming a dielectric-to-dielectric bond;
removing the first carrier; and
forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die, wherein the fan-out RDLs are electrically connected to the first die and the second die.

2. The method of claim 1 further comprising depositing a bonding layer over the first die and the first isolation material, wherein bonding the second die comprises fusion bonding the second die to the bonding layer.

3. The method of claim 1 further comprising:
depositing a bonding layer over the first die and the first isolation material; and
forming first conductive features at a top surface of the bonding layer, wherein bonding the second die comprises hybrid bonding the second die to the bonding layer.

4. The method of claim 1 further comprising depositing a second isolation material around the second die.

5. The method of claim 4 , wherein depositing the second isolation material comprises depositing the second isolation material so that a lateral portion of the second isolation material directly over the first isolation material has substantially a same thickness as a vertical portion of the second isolation material on a sidewall of the second die.

6. The method of claim 5 further comprising forming a third isolation material over and contacting the second isolation material, wherein the third isolation material and the second isolation material comprise different materials.

7. The method of claim 1 further comprising disposing a dummy die adjacent the first die or the second die.

8. The method of claim 1 further comprising after bonding the second die attaching a second carrier to an opposing surface of the second die as the first die.

9. The method of claim 1 further comprising forming a through-via extending through the first isolation material and electrically connecting the fan-out RDLs to the second die.

10. The method of claim 1 , wherein attaching the first die to the first carrier comprises attaching the first die to the first carrier using a release layer comprising an alignment mark.

11. A method comprising:
attaching a first die to a first carrier;
forming a first isolation material extending along sidewalls of the first die;
forming a bonding layer over the first die and the first isolation material;
bonding a second die directly to the bonding layer;
forming a second isolation material extending along sidewalls of the second die;
attaching a second carrier over the second die;
removing the first carrier;
forming a through via (TV) extending through the first isolation material and electrically connected to the second die; and
forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die, wherein the fan-out RDLs are electrically connected to the first die and the through via.

12. The method of claim 11 , wherein forming the second isolation material comprises depositing a lateral portion of the second isolation material on the bonding layer to have a same thickness as a vertical portion of the second isolation material on a sidewall of the second die.

13. The method of claim 12 further comprising planarizing the second isolation material to expose the second die, wherein attaching the second carrier forms a cavity between the second carrier and the second isolation material.

14. The method of claim 12 further comprising forming a third isolation material on the second isolation material, wherein a surface of the third isolation material opposite the second isolation material is substantially level.

15. The method of claim 12 , wherein the first isolation material and the second isolation material comprise different materials.

16. A method comprising:
attaching a first die on a first carrier;
attaching a second die on a second carrier;
bonding the first die to the second die while the first die is attached to the first and the second die is attached to the second carrier;
dispensing a molding compound around the first die and the second die, wherein the molding compound is dispensed between the first carrier and the second carrier;
removing the second carrier to expose a surface of the second die opposite the first die; and
forming fan-out redistribution layers over the second die and the first die, wherein the fan-out redistribution layers are electrically connected to the first die and the second die.

17. The method of claim 16 , wherein bonding the first die to the second die comprises a hybrid bonding process.

18. The method of claim 16 , further comprising forming a conductive via adjacent the second die and extending through a portion of the molding compound, wherein the conductive via is electrically connected to a first conductive feature in the first die.

19. The method of claim 18 , wherein the conductive via contacts the first conductive feature in the first die and a second conductive feature in the fan-out redistribution layers.

20. The method of claim 16 , wherein the second die comprises a through-via extending through a semiconductor substrate of the second die, and wherein forming the fan-out redistribution layers comprises forming a redistribution line on the semiconductor substrate of the second die and contacting the through-via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Sung-Feng
• Yu Chen-Hua
• Chen Ming-Fa

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/853

  On the same surface · CPC title