Vertically integrated wafers with thermal dissipation

Patent metadata

Field	Value
Publication number	US-9508685-B2
Application number	US-201414445991-A
Country	US
Kind code	B2
Filing date	Jul 29, 2014
Priority date	Jul 29, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

First claim

What is claimed is:

1. A method to fabricate a three-dimensionally integrated semiconductor device, the method comprising:
depositing an amorphous/porous silicon layer on a first surface of a first wafer;
positioning a first surface of a second wafer over the amorphous/porous silicon layer such that the first surface of the second wafer overlaps the first surface of the first wafer;
bonding the first wafer and the second wafer with the amorphous/porous silicon layer between the first wafer and the second water;
heat-treating the bonded first wafer and the second wafer effective to facilitate a reaction between a first portion of the amorphous/porous silicon layer and a first conductive coupler surface and also effective to facilitate a reaction between a second portion of the amorphous/porous silicon layer and a second conductive coupler surface to form silicide,
wherein the heat-treatment causes a volume expansion of the amorphous/porous silicon layer that results in a formation of gaps on unreacted portions of the amorphous/porous silicon layer; and

removing the unreacted portions of the amorphous/porous silicon layer between the first wafer and the second wafer.

2. The method of claim 1 , further comprising:
depositing another amorphous/porous silicon layer on the first surface of the second wafer prior to positioning the first surface of the second wafer over the amorphous/porous silicon layer such that the first surface of the second wafer overlaps the first surface of the first wafer.

3. The method of claim 2 , further comprising one of
depositing the amorphous/porous silicon layer on the first surface of the first wafer and depositing the other amorphous/porous silicon layer on the first surface of the second wafer with substantially equal thickness; or
depositing the amorphous/porous silicon layer on the first surface of the first wafer and depositing the other amorphous/porous silicon layer on the first surface of the second wafer with different thickness.

4. The method of claim 1 , wherein depositing the amorphous/porous silicon layer on the first surface of the first wafer occurs in a range from about 1 nm to about 100 μm.

5. The method of claim 1 , wherein depositing the amorphous/porous silicon layer on the first surface of the first wafer occurs by:
depositing an undoped amorphous/porous silicon layer on the first surface of the first wafer.

6. The method of claim 1 , wherein heat-treating the bonded first wafer and the second wafer occurs by a process that includes:
applying heat at a selected temperature such that the amorphous/porous silicon reacts with a metal content of the conductive coupler surfaces of the first wafer and the second wafer to form silicide.

7. The method of claim 1 , further comprising:
removing the unreacted portions of the amorphous/porous silicon layer between the first wafer and the second wafer by a process that includes employing one of wet etching, chemical etching, plasma etching, and reactive ion etching (RIE).

8. The method of claim 1 , wherein the amorphous/porous silicon layer includes a porosity in a range from about 0% porosity to about 80% porosity.

9. The method of claim 1 , further comprising:
integrating the first wafer and the second wafer using one of a front end of line (FEOL) or a back end of line (BEOL) process.

Assignees

• Empire Technology Dev Llc

Inventors

• Luo Zhijiong

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/90

  Bond pads, in general · CPC title