Method for producing an electronic device

Patent metadata

Field	Value
Publication number	US-9769931-B2
Application number	US-201615223718-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Jul 31, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A method for producing an electronic device including in a stack at least a first structure and a second structure, the structures being obtained from a first substrate and a second substrate. Marks are obtained from a pattern made on one of the substrates. Furthermore, the same supporting members are used during the bonding phase for the preparation of the marks and for the bonding phase for the assembly of the structures.

First claim

The invention claimed is:

1. A method for producing an electronic device comprising in a stack at least a first structure and a second structure, the structures being obtained from a first substrate and a second substrate, the method comprising the following steps:
forming at least one hollowed mark pattern on a second face, opposite a first face, of the first substrate;
positioning of the first face of the first substrate on a first supporting member;
positioning of a first face of the second substrate on a second supporting member;
assembling the two substrates by the second face of the first substrate and a second face, opposite the first face, of the second substrate;
separating the first substrate into two parts according to a dimension in thickness of the first substrate so as to form a first part of the first substrate remaining in position on the first supporting member, and a second part of the first substrate remaining assembled with the second substrate, the first part of the first substrate comprising a first mark formed by a first portion of the mark pattern, the second part of the first substrate comprising a second mark formed by a second portion of the mark pattern;
producing at least one electronic component on the first part of the first substrate so as to form the first structure and of at least one electronic component on the second part of the first substrate so as to form the second structure;
assembling the first structure and the second structure, the first face of the first substrate being in position on the first supporting member and the first face of the second substrate being in position on the second supporting member, by approaching the first supporting member and the second supporting member while aligning the first mark and the second mark.

2. The method according to claim 1 , wherein the first face of the first substrate is detached from the first supporting member and the first face of the second substrate is detached from the second supporting member after assembling the two substrates, and wherein the first face of the first substrate is once again attached to the first supporting member and the first face of the second substrate is once again attached to the second supporting member after producing at least one electronic component.

3. The method according to claim 1 , wherein the step of assembling the two substrates and the step of assembling the first structure and the second structure are performed by direct bonding.

4. The method according to claim 3 , wherein the step of assembling the two substrates and the step of assembling the first structure and the second structure are performed by direct bonding with the same adhesion energy.

5. The method according to claim 3 , wherein the step of assembling the two substrates and the step of assembling the first structure and the second structure are performed by direct bonding with the same pressure force applied, for both steps at the same point, by the first supporting member ( 3 ) and the second supporting member to the first faces of the first and second substrates.

6. The method according to claim 1 , wherein the step of assembling the two substrates and the step of assembling the first structure and the second structure are performed with an identical value for at least one of the parameters chosen from: the temperature of the supporting members and the substrates; the pressure, temperature, hygrometry and composition of the atmosphere.

7. The method according to claim 1 , wherein assembling the two substrates comprises approaching the first supporting member and the second supporting member, contacting the second surface of the first substrate and the second face of the second substrate so as to produce direct bonding, followed detaching the first face of the second substrate relative to the second supporting member.

8. The method according to claim 7 , wherein detaching the first face of the second substrate relative to the second supporting member is followed by detaching the first face of the first substrate relative to the first supporting member.

9. The method according to claim 1 , wherein the formation of at least one mark pattern comprises:
etching the mark pattern with a predetermined height according to a dimension in thickness of the first substrate;
forming a weakened zone, said weakened zone having a height level lower than the height of the mark pattern;
and wherein separating the first substrate into two parts comprises a treatment configured to break the weakened zone.

10. The method according to claim 9 , wherein forming the weakened zone comprises ion implantation.

11. The method according to claim 1 , wherein a plurality of hollowed mark patterns are formed on the second face of the first substrate so as to form a plurality of first marks and a plurality of second marks.

12. The method according to claim 11 , wherein a first substrate of circular cross-section is used and wherein the plurality of mark patterns comprises two primary mark patterns situated at diametrically opposed edges of the first substrate.

13. The method according to claim 11 , wherein the first substrate comprises a plurality of individual zones for producing a microelectronic chip and wherein the plurality of mark patterns comprises at least one secondary mark pattern in each individual zone.

14. The method according to claim 1 , wherein at least one of the faces situated facing the first structure and the second structure is formed by the surface of a layer of non-monocrystalline material.

Assignees

• Commissariat Energie Atomique

Inventors

• Fournel Franck
• Deguet Chrystel

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P10/128 Primary

  by direct semiconductor to semiconductor bonding · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title