Manufacturing method of semiconductor device and plasma processing apparatus

Patent metadata

Field	Value
Publication number	US-2021082766-A1
Application number	US-201916971449-A
Country	US
Kind code	A1
Filing date	Sep 13, 2019
Priority date	Sep 13, 2019
Publication date	Mar 18, 2021
Grant date	—

Abstract

In a manufacturing process of a three-dimensional structure device such as a GAA type FET or a nanosheet fork type FET having stacked channels in which channels having a shape of a wire or a sheet are stacked in a direction vertical to a substrate, a work function control metal is separately formed without expanding a space between FETs having different threshold voltages. Therefore, a first step S10 of performing anisotropic etching to open the mask material 23 until the work function control metal film 22 is exposed; a second step S11 of depositing a protective film 26; a third step S12 of performing anisotropic etching to remove the protective film while remaining the protective film deposited on sidewalls of the mask material opened in the first step; and a fourth step S13 of performing isotropic etching to selectively remove the mask material between the channels relative to the protective film and the work function control metal film are executed.

First claim

1 . A manufacturing method of a semiconductor device having stacked channels in which channels having a shape of a wire or a sheet are stacked in a direction vertical to a substrate in a gate formation region, wherein
the semiconductor device includes a first structure body including a first insulating film and the stacked channels insulated and isolated by the first insulating film, and the manufacturing method of the semiconductor device includes: a first step of forming a gate insulating film and a first work function control metal film on the first structure body, and burying the gate formation region with a mask material; a second step of performing anisotropic etching to open the mask material until the first work function control metal film covering an upper end of the first insulating film exposed by a pattern having one end located on the first insulating film in a plan view; a third step of depositing a protective film after the second step; a fourth step of performing anisotropic etching to remove the protective film while remaining the protective film deposited on sidewalls of the mask material opened in the second step; and a fifth step of performing isotropic etching after the fourth step to remove the mask material located in the pattern in a plan view selective to the protective film and the first work function control metal film.

2 . The manufacturing method of the semiconductor device according to claim 1 , further comprising:
a sixth step of removing the protective film deposited on the sidewalls of the mask material and the first work function control metal film exposed by the fifth step after the fifth step; a seventh step of removing the mask material in the gate formation region after the sixth step; and an eighth step of forming a second work function control metal film on the exposed first structure body after the seventh step.

3 . The manufacturing method of the semiconductor device according to claim 2 , wherein
the semiconductor device includes a first MOSFET having a first threshold voltage and a second MOSFET having a second threshold voltage, a first work function control metal stacked film is formed on the stacked channels of the first MOSFET, and a second work function control metal stacked film is formed on the stacked channels of the second MOSFET, and the first work function control metal stacked film and the second work function control metal stacked film have different stacked numbers or different work function control metals constituting a stacked film.

4 . The manufacturing method of the semiconductor device according to claim 1 , wherein
the semiconductor device includes a first MOSFET having a first threshold voltage and a second MOSFET having a second threshold voltage, a threshold voltage adjusting film is formed between the gate insulating film and the first work function control metal film in the first step, and the method includes a step of removing the threshold voltage adjusting film from the stacked channels of the first MOSFET, and remaining the threshold voltage adjusting film on the stacked channels of the second MOSFET and performing a heat treatment to the threshold voltage adjusting film.

5 . The manufacturing method of the semiconductor device according to claim 1 , wherein
the second to fifth steps are continuously performed in the same plasma processing apparatus.

6 . A manufacturing method of a semiconductor device having stacked channels in which channels having a shape of a wire or a sheet are stacked in a direction vertical to a substrate in a gate formation region, the manufacturing method comprising:
a first step of forming a gate insulating film and a first work function control metal film in a manner of surrounding the channels, and burying the gate formation region with a mask material; a second step of performing anisotropic etching to open the mask material until the first work function control metal film covering an upper end of a channel located in an uppermost layer of the stacked channels is exposed by a pattern having one end located on the stacked channels in a plan view; a third step of depositing a protective film after the second step; a fourth step of performing anisotropic etching to remove the protective film while remaining the protective film deposited on sidewalls of the mask material opened in the second step; a fifth step of performing anisotropic etching to open the mask material located in the pattern in a plan view after the fourth step; and a sixth step of performing isotropic etching after the fifth step to remove the mask material between the channels of the stacked channels located in the pattern in a plan view selective to the protective film and the first work function control metal film.

7 . The manufacturing method of the semiconductor device according to claim 6 , further comprising:
a seventh step of performing isotropic etching after the sixth step to remove the protective film deposited on the sidewalls of the mask material and to remove the mask material selective to the first work function control metal film.

8 . The manufacturing method of the semiconductor device according to claim 7 , wherein
the semiconductor device includes a first MOSFET having a first threshold voltage and a second MOSFET having a second threshold voltage, the stacked channels of the first MOSFET and the stacked channels of the second MOSFET are disposed adjacent to each other on the substrate, and an end portion of the pattern is located on the stacked channels of the first MOSFET, and an end portion of the pattern is located closer to the stacked channels of the second MOSFET than a center of the channels of the stacked channels.

9 . The manufacturing method of the semiconductor device according to claim 8 , further comprising:
an eighth step of removing the first work function control metal film exposed by the seventh step after the seventh step; a ninth process of removing the mask material in the gate formation region after the eighth step; and a tenth process of forming a second work function control metal film in a manner of surrounding the exposed channel after the ninth process.

10 . The manufacturing method of the semiconductor device according to claim 9 , wherein
the first work function control metal stacked film is formed on the stacked channels of the first MOSFET, and the second work function control metal stacked film is formed on the stacked channels of the second MOSFET, and the first work function control metal stacked film and the second work function control metal stacked film have different stacked numbers or different work function control metals constituting a stacked film.

11 . The manufacturing method of the semiconductor device according to claim 8 , wherein
a threshold voltage adjusting film is formed between the gate insulating film and the first work function control metal film in the first step, and the method includes a step of removing the threshold voltage adjusting film from the stacked channels of the first MOSFET, and remaining the threshold voltage adjusting film on the stacked channels of the second MOSFET and performing a heat treatment to the threshold voltage adjusting film.

12 . The manufacturing method of the semiconductor device according to claim 7 , wherein
the second to seventh steps are continuously performed in the same plasma processing apparatus.

13 . A plasma processing apparatus that performs plasma processing on a semiconductor substrate, the semiconductor substrate having stacked channels having a shape of a wire or a sheet in a gate formation region, the channels bein

Assignees

• Hitachi High Tech Corp

Inventors

• Miura Makoto
• Sato Kiyohiko
• Sonoda Yasushi
• Sakai Satoshi

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title