Gate to source/drain contact links implemented in metallization layer contacting device layer
US-2026096141-A1 · Apr 2, 2026 · US
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Guler Leonard patents
Guler Leonard is listed as an inventor on 46 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Guler Leonard |
| Total patents | 46 |
| First publication | Sep 19, 2019 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Frontside feedthrough connections
US-2025385166-A1 · Dec 18, 2025 · US
SRAM with channel count contrast for greater read stability
US-12484207-B2 · Nov 25, 2025 · US
Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material
US-12426316-B2 · Sep 23, 2025 · US
Cavity spacer for nanowire transistors
US-2025280567-A1 · Sep 4, 2025 · US
Extreme ultraviolet lithography patterning with assist features
US-12405526-B2 · Sep 2, 2025 · US
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
US-12369393-B2 · Jul 22, 2025 · US
Dielectric isolation layer between a nanowire transistor and a substrate
US-12349394-B2 · Jul 1, 2025 · US
Cavity spacer for nanowire transistors
US-12328905-B2 · Jun 10, 2025 · US
Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material
US-2025176225-A2 · May 29, 2025 · US
Recent patents
Latest publications not already listed above.
Epi height reduction for improved transistor performance
US-2025113564-A1 · Apr 3, 2025 · US
Backside source/drain transistor contact flow with selective etch materials for robust connectivity
US-2025113580-A1 · Apr 3, 2025 · US
Stacked nanowire transistor structures with isolation regions bound by gate cuts
US-2025113563-A1 · Apr 3, 2025 · US
Self-aligned via patterning for backside interconnects
US-2024404917-A1 · Dec 5, 2024 · US
Self aligned gratings for tight pitch interconnects and methods of fabrication
US-12131991-B2 · Oct 29, 2024 · US
Cavity Spacer for Nanowire Transistors
US-2024347595-A1 · Oct 17, 2024 · US
Transistor with channel-symmetric gate
US-2024332290-A1 · Oct 3, 2024 · US
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
US-2024266353-A1 · Aug 8, 2024 · US
Methods and apparatus to reduce extreme ultraviolet light for photolithography
US-2024241446-A1 · Jul 18, 2024 · US
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
US-12002810-B2 · Jun 4, 2024 · US
Dielectric isolation layer between a nanowire transistor and a substrate
US-2024145598-A1 · May 2, 2024 · US
Cavity spacer for nanowire transistors
US-11929396-B2 · Mar 12, 2024 · US
Dielectric isolation layer between a nanowire transistor and a substrate
US-11901458-B2 · Feb 13, 2024 · US
Recessed transistor terminal via jumpers
US-2023320057-A1 · Oct 5, 2023 · US
Sram with nanoribbon width modulation for greater read stability
US-2023209797-A1 · Jun 29, 2023 · US
Sram with dipole dopant threshold voltage modulation for greater read stability
US-2023209799-A1 · Jun 29, 2023 · US
Sram with channel count contrast for greater read stability
US-2023209798-A1 · Jun 29, 2023 · US
Single-sided nanosheet transistors
US-2023114214-A1 · Apr 13, 2023 · US
Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material
US-2023089815-A1 · Mar 23, 2023 · US
Non-planar transistors with channel regions having varying widths
US-11569231-B2 · Jan 31, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 46 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 40 |
| H10D30/6735 | 31 |
| H10D30/6757 | 29 |
| H10D62/121 | 28 |
| H10D30/43 | 26 |