Semiconductor Device and Method

Patent metadata

Field	Value
Publication number	US-2021376076-A1
Application number	US-202017127095-A
Country	US
Kind code	A1
Filing date	Dec 18, 2020
Priority date	May 27, 2020
Publication date	Dec 2, 2021
Grant date	—

Abstract

In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

First claim

What is claimed is:

1 . A method comprising:
forming a forksheet structure over a substrate; forming a power rail contact adjacent the forksheet structure; forming an isolation region on the power rail contact, the forksheet structure protruding from the isolation region; growing a first source/drain region in the forksheet structure; depositing an interlayer dielectric (ILD) on the first source/drain region; and forming a source/drain contact through the ILD and the isolation region, the source/drain contact connected to the first source/drain region and the power rail contact.

2 . The method of claim 1 , wherein the forksheet structure comprises first nanostructures, second nanostructures, and a dielectric wall between the first nanostructures and the second nanostructures, the first source/drain region adjoining the first nanostructures, the method further comprising:
growing a second source/drain region in the forksheet structure, the second source/drain region adjoining the second nanostructures, the dielectric wall disposed between the first source/drain region and the second source/drain region.

3 . The method of claim 2 further comprising:
forming a first gate structure around the first nanostructures; and
forming a second gate structure around the second nanostructures, the second gate structure connected to the first gate structure.

4 . The method of claim 2 , wherein the first nano structures, the second nanostructures, and the dielectric wall have parallel longitudinal axes in a first direction, and the dielectric wall is disposed between the first source/drain region and the second source/drain region in a second direction, the first direction being perpendicular to the second direction.

5 . The method of claim 1 , wherein forming the power rail contact comprises:
depositing a conductive layer on and adjacent the forksheet structure; and removing portions of the conductive layer on the forksheet structure, the power rail contact comprising portions of the conductive layer remaining adjacent the forksheet structure.

6 . The method of claim 1 , wherein forming the isolation region comprises:
depositing a dielectric layer on the forksheet structure and the power rail contact; and removing portions of the dielectric layer on the forksheet structure, the isolation region comprising portions of the dielectric layer remaining on the power rail contact.

7 . The method of claim 1 , wherein forming the forksheet structure comprises:
forming a first fin structure and a second fin structure extending from the substrate; depositing a dielectric layer over and between the first fin structure and the second fin structure; and removing portions of the dielectric layer over the first fin structure and the second fin structure to form a dielectric wall comprising portions of the dielectric layer remaining between the first fin structure and the second fin structure.

8 . The method of claim 1 further comprising:
forming a dielectric fin on the isolation region, the first source/drain region being separated from the dielectric fin after growing the first source/drain region; and
after growing the first source/drain region, depositing a dielectric layer between the dielectric fin and the first source/drain region, the ILD deposited on the dielectric layer.

9 . The method of claim 8 , wherein forming the source/drain contact comprises:
etching an opening through the ILD, the dielectric layer, and the isolation region, portions of the opening in the ILD exposing a top surface of the first source/drain region, portions of the opening in the dielectric layer exposing a side surface of the first source/drain region, portions of the opening in the isolation region exposing the power rail contact; forming a metal-semiconductor alloy region on the first source/drain region and in the opening, portions of the metal-semiconductor alloy region on the top surface of the first source/drain region having a first thickness, portions of the metal-semiconductor alloy region on the side surface of the first source/drain region having a second thickness, the first thickness being greater than or equal to the second thickness; and forming the source/drain contact on the metal-semiconductor alloy region and portions of the power rail contact exposed by the opening.

10 . A device comprising:
a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

11 . The device of claim 10 further comprising:
a liner layer disposed between the first dielectric fin and each of the isolation region and the power rail contact.

12 . The device of claim 10 further comprising:
a metal-semiconductor alloy region between the source/drain contact and the first source/drain region, portions of the metal-semiconductor alloy region on the top surface of the first source/drain region having a first thickness, portions of the metal-semiconductor alloy region on the side surface of the first source/drain region having a second thickness, the first thickness being greater than or equal to the second thickness.

13 . The device of claim 12 , wherein the first thickness and the second thickness are in a range of 2.5 nm to 7.5 nm.

14 . The device of claim 10 , wherein back-side surfaces of the power rail contact and the second dielectric fin are coplanar.

15 . The device of claim 14 further comprising:
a second dielectric layer on the back-side surfaces of the power rail contact and the first dielectric fin; and
a power rail line in the second dielectric layer, the power rail line connected to the power rail contact.

16 . The device of claim 14 , wherein surfaces of the power rail contact are free of metal-semiconductor alloy regions.

17 . The device of claim 10 further comprising:
a dielectric layer laterally disposed between the first dielectric fin and the first source/drain region, the source/drain contact extending through the dielectric layer; and
an interlayer dielectric (ILD) on the dielectric layer, the first dielectric fin, and the second dielectric fin, the source/drain contact extending through the ILD.

18 . A device comprising:
a first interconnect structure comprising metallization patterns; a second interconnect structure comprising a power rail line; a device layer between the first interconnect structure and the second interconnect structure, the device layer comprising:
a transistor comprising a source/drain region;
a power rail contact connected to the power rail line; and
a source/drain contact connected to the power rail contact, the source/drain region, and the metallization patterns.

19 . The device of claim 18 , wherein the device layer further comprises:
an isolation region isolating the transistor from other transistors of the device layer, the power rail contact buried in the isolation region.

20 . The device of claim 18 , wherein the source/drain region has a faceted top surface and a faceted side surface, the source/drain contact extending along the faceted top surface and the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Huan-Chieh
• Chuang Cheng-Chi
• Chang Shang-Wen
• Chiu Yi-Hsun
• Wang Pei-Yu
• Tsai Ching-Wei
• Wang Chih-Hao

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title