Minimum width device for power saving

Patent metadata

Field	Value
Publication number	US-2020212037-A1
Application number	US-201916238223-A
Country	US
Kind code	A1
Filing date	Jan 2, 2019
Priority date	Jan 2, 2019
Publication date	Jul 2, 2020
Grant date	—

Abstract

A semiconductor structure is provided that includes a first FinFET device for low power applications and a second FinFET device for non-low power applications. The first FinFET device has an active fin height, i.e., channel height, which is less that an active fin height of the second FinFET device. The active fin height adjustment is achieved utilizing an isolation structure that has a constant height in the region including the first FinFET device and the region including the second FinFET device.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
at least one first fin structure located in a first region of a semiconductor substrate; at least one second fin structure located in a second region of the semiconductor structure; an isolation structure located on the semiconductor substrate and laterally surrounding a lower portion of the first fin structure and a lower portion of the second fin structure, wherein the isolation structure has a constant thickness across the first region and the second region, and the at least one first fin structure has a first active fin height and the at least one second fin structure has a second active fin height that is greater than the first active height.

2 . The semiconductor structure of claim 1 , wherein the at least one first fin structure and the at least one second fin structure are composed of a compositionally same semiconductor material.

3 . The semiconductor structure of claim 1 , wherein the at least one first fin structure has a first total fin height and the at least one second fin structure has a second total fin height that is greater than the first total fin height.

4 . The semiconductor structure of claim 1 , further comprising a first functional gate structure located on the isolation structure and contacting an upper portion of the at least one fin structure, and a second functional gate structure located on the isolation structure and contacting an upper portion of the at least one second fin structure.

5 . The semiconductor structure of claim 4 , further comprising a dielectric structure laterally surrounding the first functional gate structure and the second functional gate structure.

6 . The semiconductor structure of claim 5 , wherein the dielectric structure has a topmost surface that is coplanar with a topmost surface of the first functional gate structure and a topmost surface of the second functional gate structure.

7 . The semiconductor structure of claim 5 , wherein the dielectric structure comprises a gate spacer and an interlayer dielectric (ILD) material.

8 . The semiconductor structure of claim 1 , wherein the first region is an n-type field effect transistor (nFET) device region and the second region is a p-type field effect transistor device region.

9 . The semiconductor structure of claim 1 , wherein the first region is a p-type field effect transistor (nFET) device region and the second region is an n-type field effect transistor device region.

10 . A method of forming a semiconductor structure, the method comprising:
forming an opening in a first region of a semiconductor substrate composed of a first semiconductor material; forming a second semiconductor material that is compositionally different from the first semiconductor material of the semiconductor substrate in the opening, wherein the second semiconductor material has a topmost surface that is coplanar with a topmost surface of the semiconductor substrate; forming at least one semiconductor fin stack including a lower fin portion composed of the first semiconductor material and an upper fin portion composed of the second semiconductor material in the first region of the semiconductor substrate, and at least one second fin structure composed entirely of a fin portion composed of the first semiconductor material in a second region of the semiconductor substrate; forming an isolation structure surrounding a bottom portion of the at least one first semiconductor fin stack and a bottom portion of the at least one second fin structure; and removing the upper fin portion entirely from the semiconductor fin stack to provide at least one first fin structure in the first region, wherein the at least one fin structure has a first active fin height that is less than an active fin height of the at least one second fin structure.

11 . The method of claim 10 , wherein the isolation structure has a constant thickness across the first region and the second region.

12 . The method of claim 10 , wherein the first semiconductor material is composed of silicon, and the second semiconductor material is composed of a silicon germanium alloy.

13 . The method of claim 10 , wherein the forming of the opening comprises:
forming a hard mask layer on the semiconductor substrate; and lithography patterning the hard mask layer and an upper portion of the semiconductor substrate.

14 . The method of claim 10 , wherein the forming of the second semiconductor material comprises epitaxial growth and planarization.

15 . The method of claim 10 , wherein the forming of the at least semiconductor fin stack and the second fin structure comprises a patterning process.

16 . The method of claim 10 , wherein the removing of the second fin portion from the at least one semiconductor fin stack comprises a selective etching process.

17 . The method of claim 10 , wherein the at least one first fin structure and the at least one second fin structure are entirely composed of the first semiconductor material.

18 . The method of claim 10 , wherein the at least one first fin structure has a first total fin height and the at least one second fin structure has a second total fin height that is greater than the first total fin height.

19 . The method of claim 10 , further comprising forming a first functional gate structure on the isolation structure and contacting an upper portion of the at least one first fin structure, and a second functional gate structure on the isolation structure and contacting an upper portion of the at least one second fin structure.

20 . The method of claim 19 , further comprising forming a dielectric structure laterally surrounding the first functional gate structure and the second functional gate structure.

Assignees

• IBM

Inventors

• Yu Lan
• Wang Junli
• Wu Heng
• Bao Ruqiang
• Guo Dechao

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title