Package structures with patterned die backside layer

Patent metadata

Field	Value
Publication number	US-12598989-B2
Application number	US-202217710507-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

First claim

What is claimed is:

1 . A microelectronic die package structure comprising:
a substrate; a die comprising a first side and a second side, wherein the first side of the die is coupled to the substrate; and a die backside layer on the second side of the die, wherein the die backside layer comprises a plurality of unfilled grooves in the die backside layer, each of the unfilled grooves comprising an opening at a surface of the die backside layer opposite the second side of the die and extending at least partially through the die backside layer, wherein at least one of the unfilled grooves extends completely through the die backside layer.

2 . The microelectronic die package structure of claim 1 , wherein at least one of the unfilled grooves does not extend completely through the die backside layer.

3 . The microelectronic die package structure of claim 1 , wherein a distance between each of the plurality of unfilled grooves is substantially the same.

4 . The microelectronic die package structure of claim 3 , wherein the unfilled grooves extend across at least one of a length or a width of the die backside layer, and wherein the unfilled grooves comprise a uniform depth and a uniform width.

5 . The microelectronic die package structure of claim 1 , wherein the die backside layer comprises at least one of copper, aluminum, silver, gold, nickel, diamond, aluminum nitride, silicon carbide, or combinations thereof.

6 . The microelectronic die package structure of claim 1 , further comprising: an intermediate layer between the die backside layer and the second side of the die, wherein the intermediate layer comprises at least one of titanium, nickel, vanadium, gold, or nitrogen, and wherein the intermediate layer comprises a thickness of between 10 nm to 500 nm.

7 . The microelectronic die package structure of claim 6 , wherein at least one of the unfilled grooves extends through the die backside layer and the intermediate layer.

8 . The microelectronic die package structure of claim 1 , wherein the die backside layer comprises a thickness between 50 microns and 500 microns.

9 . The microelectronic die package structure of claim 1 , wherein a series of concentric unfilled grooves extend at least partially within the die backside layer.

10 . A computer system comprising;
a power supply; one or more integrated circuit packages coupled to the power supply, wherein at least one of the integrated circuit packages comprises:
a substrate comprising a surface;
one or more conductive interconnect structures on the surface of the substrate;
a die comprising a first side and a second side, wherein the first side of the die is coupled to the one or more conductive interconnect structures; and
a die backside layer on the second side of the die, wherein the die backside layer comprises one or more unfilled grooves comprising an opening at a surface of the die backside layer opposite the second side of the die and extending at least partially through the die backside layer, wherein a length of the opening is the same as at least one of a length of the die or a width of the die.

11 . The computer system of claim 10 , wherein a thickness of the die backside layer is between 50 microns to 500 microns.

12 . The computer system of claim 10 , wherein a series of concentric unfilled grooves extend at least partially within the die backside layer.

13 . The computer system of claim 12 , further comprising an intermediate layer between the die backside layer and the second side of the die, wherein the series of concentric unfilled grooves extends completely through the die backside layer and completely through the intermediate layer.

Assignees

• Intel Corp

Inventors

• Liu Pilin
• Eid Feras
• Baker Michael
• Li Wenhao
• Li Zhaozhi

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title