Methods of forming multi-chip package structures

Patent metadata

Field	Value
Publication number	US-10553548-B2
Application number	US-201715635555-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Jun 28, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate, a second die disposed on the substrate, a molding compound disposed between the first die and the second die, wherein the molding compound is disposed on a top surface of the substrate. An epoxy material is disposed between a top portion of a sidewall of the first die and the molding compound, and a thermal interface material (TIM) is disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate.

First claim

What is claimed is:

1. A microelectronic package structure comprising:
a first die on a substrate;
a second die on the substrate adjacent the first die;
a first portion of an epoxy material on an entire length of a sidewall of the first die and directly on a top surface of the substrate, wherein a first sidewall of the first portion of the epoxy material is opposite a second sidewall of the first portion of the epoxy material, wherein the first sidewall and the second sidewall of the first portion of the epoxy material are parallel to a first sidewall of the first die;
a second portion of the epoxy material on a sidewall of the second die and directly on the top surface of the substrate;
a molding compound, wherein a portion of the molding compound is between the first portion and the second portion of the epoxy material and is between the first die and the second die, wherein the portion of the molding compound is directly on the top surface of the substrate, wherein the portion of the molding compound is adjacent a second sidewall of the first die, opposite the first sidewall of the first die,
wherein a top surface of the portion of the molding compound, a top surface of the first portion of the epoxy material, a top surface of the second portion of the epoxy material, a top surface of the first die and a top surface of the second die share a common plane with each other; and
a thermal interface material (TIM) directly on the top surface of the portion of the molding compound, directly on the top surfaces of the first portion and the second portion of the epoxy material, and directly on the top surfaces of the first die and the second die.

2. The microelectronic package structure of claim 1 wherein the portion of the molding compound comprises a first portion, and wherein a second portion of the molding compound is adjacent the first sidewall of the first die, wherein a first sidewall of the second portion of the molding compound and a second sidewall, opposite the first sidewall, of the second portion of the molding compound are parallel with the first sidewall of the first die, and wherein the (TIM) is on a top surface of the second portion of the molding compound, wherein the top surface of the second portion of the molding compound is coplanar with the top surface of the first portion of the epoxy material.

3. The microelectronic package structure of claim 1 wherein a cooling solution is on a top surface of the TIM.

4. The microelectronic package structure of claim 1 wherein the molding compound comprises an epoxy molding compound.

5. The microelectronic package structure of claim 1 wherein the epoxy material comprises an underfill material, wherein a third portion of the epoxy material is on an entire length of the second sidewall of the first die wherein sidewalls of the third portion are parallel with the second sidewall of the first die.

6. The microelectronic package structure of claim 1 wherein the sidewall of the second die comprises a first sidewall of the second die, and wherein an additional portion of the molding compound is adjacent a second sidewall, opposite the first sidewall, of the second die, wherein sidewalls of the additional portion of the molding compound are parallel with the second sidewall of the second die, and wherein a top surface of the additional portion of the molding compound is coplanar with a top surface of the third portion of the epoxy material.

7. The microelectronic package structure of claim 6 wherein a width of the top surface of the third portion of the epoxy material and a width of the top surface of the first portion of the epoxy material are substantially equal.

8. The microelectronic package structure of claim 1 wherein a plurality of interconnect structures is beneath the second die, and is surrounded by the epoxy material.

Assignees

• Intel Corp

Inventors

• Neal Nicholas
• Haehn Nicholas S

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title