Package-on-package structure with through molding via

Patent metadata

Field	Value
Publication number	US-9780076-B2
Application number	US-201615356268-A
Country	US
Kind code	B2
Filing date	Nov 18, 2016
Priority date	Sep 12, 2013
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

First claim

What is claimed is:

1. A method for forming a device, comprising:
forming a molding compound on a surface of a substrate; and
patterning the molding compound to define:
a first opening extending through the molding compound and exposing a conductive connector on the surface of the substrate; and
a second opening extending through the molding compound, wherein the second opening is free of any conductive features disposed therein, wherein tops and bottoms of the first opening and the second opening are substantially level, and wherein the first opening and the second opening have substantially a same shape in a top-down view.

2. The method of claim 1 , wherein a first area of the first opening in a plan view is less than a second area of the second opening.

3. The method of claim 1 further comprising:
bonding a die to the surface of the substrate, wherein forming the molding compound comprises encapsulating the die in the molding compound; and
after patterning the molding compound, bonding a package to the surface of the substrate, wherein the die and the molding compound are disposed between the substrate and the package.

4. The method of claim 3 , wherein bonding the package to the surface of the substrate comprises disposing a first solder region of the package in the first opening, wherein the first solder region is electrically connected to the conductive connector.

5. The method of claim 3 , wherein the first opening is disposed between the second opening and the die.

6. The method of claim 1 , wherein the conductive connector comprises a second solder region disposed on a conductive land, wherein a sidewall of the second opening contacts a sidewall of the second solder region.

7. The method of claim 1 , wherein patterning the second opening comprises a laser ablation process.

8. A method comprising:
disposing a semiconductor die and a plurality of connectors on a surface of a substrate;
dispensing a molding compound along sidewalls of the semiconductor die and the plurality of connectors; and
patterning a first opening extending through the molding compound, wherein a continuous sidewall of the first opening completely encircles at least two of the plurality of connectors, and wherein no molding compound is disposed between any of the at least two of the plurality of connectors.

9. The method of claim 8 , further comprising a second opening extending through the molding compound, wherein one of the plurality of connectors is disposed in the second opening, and wherein a portion of the molding compound is disposed between the first opening and the second opening.

10. The method of claim 9 , wherein the first opening is disposed between the semiconductor die and the second opening.

11. The method of claim 9 , wherein the second opening is smaller than the first opening in a top-down view.

12. The method of claim 8 further comprising bonding a package to the surface of the substrate, wherein bonding the package comprises bonding conductive features of the package directly to the plurality of connectors on the surface of the substrate.

13. The method of claim 8 , wherein dispensing the molding compound comprises disposing a portion of the molding compound directly over the plurality of connectors, and wherein patterning the first opening comprises exposing the at least two of the plurality of connectors.

14. The method of claim 8 , wherein patterning the molding compound further comprises exposing a top surface of the die, and wherein after patterning the molding compound, a top surface of the molding compound is higher than tops of the plurality of connectors.

15. A device package comprising:
a semiconductor die on a surface of a substrate;
a first conductive connector and a second conductive connector on the surface of the substrate;
a molding compound disposed around the semiconductor die, the first conductive connector, and the second conductive connector;
a first opening extending through the molding compound, wherein the first conductive connector is disposed in the first opening;
a second opening extending through the molding compound, wherein the second conductive connector is disposed in the second opening; and
a cavity extending through the molding compound, wherein no conductive connectors are disposed in the cavity, and wherein an entirety of the cavity is disposed between the first opening and the second opening in a top-down view of the device package.

16. The device package of claim 15 further comprising a package bonded to the surface of the substrate by the first conductive connector and the second conductive connector, wherein the semiconductor die is disposed between the substrate and the package.

17. The device package of claim 16 , wherein the package comprises a package substrate having a through via extending through an additional substrate, and wherein the through via provides a conduction path from the first conductive connector to a surface of the package substrate opposite the semiconductor die.

18. The device package of claim 15 , wherein bottoms of the cavity, the second opening, and the first opening are substantially level.

19. The device package of claim 15 , wherein the cavity is smaller than the first opening and the second opening in the top-down view.

20. The device package of claim 15 , wherein tops of the first opening, the second opening, and the cavity are substantially level with a top surface of the semiconductor die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yew Ming-Chih
• Li Fu-Jen
• Lin Po-Yao
• Liu Kuo-Chuan

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title