Method of forming a plurality of bumps on a substrate and method of forming a chip package

Patent metadata

Field	Value
Publication number	US-9318455-B2
Application number	US-201414151855-A
Country	US
Kind code	B2
Filing date	Jan 10, 2014
Priority date	Nov 30, 2011
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A method of forming a plurality of bump structures on a substrate includes forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate. The method further includes forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures. The method further includes plating a plurality of layers in the openings, wherein the metal layers are part of the plurality of bump structures. The method further includes planarizing the plurality of bump structures after the metal layers are plated to a targeted height from a surface of the substrate.

First claim

What is claimed is:

1. A method of forming a plurality of bump structures on a substrate, comprising:
forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate;
forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures;
plating a plurality of layers in each opening of the openings, wherein the layers are part of the plurality of bump structures, wherein a height of the plurality of layers in a corresponding opening of the openings varies from a center of the substrate to an edge of the substrate; and
planarizing the plurality of bump structures after the layers are plated to a targeted height from a surface of the substrate.

2. The method of claim 1 , wherein the plurality of layers comprises a copper layer, a metal layer, and a solder layer, wherein the metal layer is between the copper layer and the solder layer, and the copper layer contacts the UBM layer.

3. A method of forming a chip package, comprising:
providing a first chip with a first plurality of bump structures, wherein the first plurality of bump structures are planarized to a first height;
providing a substrate with a second plurality of bump structures, wherein the second plurality of bump structures are planarized to a second height; and
bonding the first and second plurality of bump structures together, wherein a standoff distance exists between the first chip and the substrate, and a thickness of a solder layer between a bump structure of the first plurality of bump structures to a corresponding bump structure of the second plurality of bump structures varies across the chip package.

4. The method of claim 3 , further comprising
underfilling a space between the first chip and the substrate with an underfill material.

5. The method of claim 3 , further comprising:
providing a second chip with a third plurality of bump structures, wherein the third plurality of bump structures are planarized to a third height; and
bonding the third plurality of bump structures with the second plurality of bump structures on the substrate, wherein a standoff height between the second chip and the substrate is substantially equal to the standoff distance.

6. The method of claim 5 , wherein a fixed volume of underfill material is used to underfill a first space between the first chip and the substrate and to underfill a second space between the second chip and the substrate.

7. The method of claim 4 , wherein the underfilling does not form a void or a fillet.

8. A method of forming a chip package, the method comprising:
forming a plurality of bump structures on a first chip, wherein forming the plurality of bump structures comprises:
forming a solder layer in each bump structure of the plurality of bump structures, wherein a solder layer in a first bump structure of the plurality of bump structures near a center of the first chip is thicker than a solder layer in a second bump structure of the plurality of bump structures near an edge of the first chip, and a solder layer in a third bump structure of the plurality of bump structures positioned between the first bump structure and the second bump structure is thicker than the solder layer of the second bump structure and thinner than a solder layer of the first bump structure.

9. The method of claim 8 , wherein forming the plurality of bump structures comprises forming an under bump metallurgy (UBM) layer between a substrate of the first chip and the solder layer, wherein the UBM layer comprises a diffusion barrier layer and a seed layer, and the seed layer is between the diffusion barrier layer and the solder layer.

10. The method of claim 8 , further comprising planarizing the solder layer in each bump structure of the plurality of bump structures.

11. The method of claim 10 , wherein planarizing the solder layer comprises grinding the solder layer.

12. The method of claim 8 , further comprising bonding the solder layer in each bump structure of the plurality of bump structures to a respective conductive structure on a substrate.

13. The method of claim 12 , wherein bonding the solder layer comprises forming a standoff distance between the first chip and the substrate, and a variation of the standoff distance across the first chip is less than or equal to about 3 microns (μm).

14. The method of claim 12 , wherein bonding the solder layer comprises bonding the solder layer to a respective contact pad on the substrate.

15. The method of claim 12 , further comprises filling a space between the first chip and the substrate with an underfill material.

16. The method of claim 15 , wherein filling the space comprising filling the space with the underfill material being free of voids or fillets.

17. The method of claim 8 , further comprising forming a photoresist material between adjacent bump structures of the plurality of bump structures, wherein the photoresist material defines an opening above each bump structure of the plurality of bump structures.

18. The method of claim 17 , wherein forming the solder layer comprises:
forming a solder material in the opening above each bump structure of the plurality of bump structures; and
planarizing the solder material to form the solder layer.

19. The method of claim 18 , further comprising removing the photoresist layer between the adjacent bump structures of the plurality of bump structures, wherein the adjacent bump structures of the plurality of bump structures have the planarized solder material.

20. The method of claim 8 , wherein forming the plurality of bump structures further comprises forming a copper layer in each bump structure of the plurality of bump structures, wherein a copper layer in a first bump structure of the plurality of bump structures near a center of the first chip is thinner than a copper layer in a second bump structure of the plurality of bump structures near an edge of the first chip, and a copper layer in a third bump structure of the plurality of bump structures positioned between the first bump structure and the second bump structure is thinner than the solder layer of the second bump structure and thicker than a solder layer of the first bump structure.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lin Jing-Cheng
• Tsai Po-Hao

Classifications

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title