Dry etching of semiconductor structures with fluorine-containing gases

Patent metadata

Field	Value
Publication number	US-12471344-B2
Application number	US-202117461186-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Aug 30, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

First claim

What is claimed is:

1 . A method, comprising:
forming a fin structure with a stacked fin portion on a substrate, wherein the stacked fin portion comprises a first semiconductor layer and a second semiconductor layer, and wherein the second semiconductor layer comprises germanium; forming a protective layer on top and sidewall surfaces of the fin structure; etching the protective layer and the fin structure to form a first opening; and etching, through the first opening, a portion of the second semiconductor layer with a fluorine-containing gas to form a second opening, wherein the second opening is surrounded by the protective layer, the first semiconductor layer, and the second semiconductor layer.

2 . The method of claim 1 , wherein the forming the fin structure comprises forming the first semiconductor layer with silicon.

3 . The method of claim 1 , wherein the forming the fin structure comprises forming the second semiconductor layer with silicon germanium having germanium in a range from about 40 atomic percent to about 100 atomic percent.

4 . The method of claim 1 , further comprising delivering the fluorine-containing gas to the fin structure at a flow rate ranging from about 1 sccm to about 500 sccm.

5 . The method of claim 1 , wherein the etching the portion of the second semiconductor layer comprises etching the portion of the second semiconductor layer at a temperature ranging from about −20° C. to about 350° C.

6 . The method of claim 1 , wherein the etching the portion of the second semiconductor layer comprises etching the portion of the second semiconductor layer under a pressure ranging from about 10 mTorr to about 10000 mTorr.

7 . The method of claim 1 , further comprising:
removing the portion of the second semiconductor layer with the fluorine-containing gas at a first etch rate, wherein the first semiconductor layer and a gate spacer structure above the first and second semiconductor layers have a second etch rate with the fluorine-containing gas, and wherein a ratio of the first etch rate to the second etch rate ranges from about 10 to about 500.

8 . The method of claim 1 , wherein the fluorine-containing gas comprises at least one of fluorine, hydrogen fluoride, chlorine trifluoride, a fluorine radical, and a nitrogen trifluoride radical.

9 . A method, comprising:
forming a fin structure with a stacked fin portion on a substrate, wherein the stacked fin portion comprises a first set of semiconductor layers and a second set of semiconductor layers, and wherein the second set of semiconductor layers comprise germanium; etching the fin structure to form a first opening; removing, through the first opening via an etching process, a first portion of the second set of semiconductor layers with a fluorine-containing gas to form a second opening in the second set of semiconductor layers, wherein:
the first portion of the second set of semiconductor layers is etched at a first etch rate during the etching process;
the first set of semiconductor layers and a gate spacer structure above the first and second set of semiconductor layers have a second etch rate with the fluorine-containing gas; and
a ratio of the first etch rate to the second etch rate ranges from about 10 to about 500;
depositing a dielectric material in the second opening to form an inner spacer structure; and etching a second portion of the second set of semiconductor layers adjacent to dielectric material of the inner spacer structure with the fluorine-containing gas.

10 . The method of claim 9 , further comprising forming a gate structure wrapping around the first set of semiconductor layers.

11 . The method of claim 9 , wherein the forming the fin structure comprises forming the second set of semiconductor layers with silicon germanium having germanium in a range from about 40 atomic percent to about 100 atomic percent.

12 . The method of claim 9 , further comprising delivering the fluorine-containing gas to the fin structure at a flow rate ranging from about 1 sccm to about 500 sccm.

13 . The method of claim 9 , wherein the etching the first portion of the second set of semiconductor layers comprises etching the first portion of the second set of semiconductor layers at a temperature ranging from about −20° C. to about 350° C.

14 . The method of claim 9 , wherein the etching the first portion of the second set of semiconductor layers comprises etching the first portion of the second set of semiconductor layers under a pressure ranging from about 10 mTorr to about 10000 mTorr.

15 . The method of claim 9 , wherein the fluorine-containing gas comprises at least one of fluorine, hydrogen fluoride, chlorine trifluoride, a fluorine radical, and a nitrogen trifluoride radical.

16 . A method, comprising:
forming a stack of semiconductor layers on a substrate, wherein the stack of semiconductor layers comprises first and second semiconductor layers stacked in an alternating configuration; forming a protective layer on top and sidewall surfaces of the stack of semiconductor layers; forming a first opening in the stack of semiconductor layers; etching, through the first opening, a portion of the second semiconductor layer with a fluorine-containing gas to form a second opening; and forming an inner spacer structure in the second opening, wherein the inner spacer structure is in contact with the protective layer, the first semiconductor layer, and the second semiconductor layer.

17 . The method of claim 16 , wherein the forming the stack of semiconductor layers comprises forming the first semiconductor layer with silicon.

18 . The method of claim 16 , wherein the forming the stack of semiconductor layers comprises forming the second semiconductor layer with silicon germanium having germanium in a range from about 40 atomic percent to about 100 atomic percent.

19 . The method of claim 16 , wherein the etching the portion of the second semiconductor layer comprises removing the portion of the second semiconductor layer with a dry etching process.

20 . The method of claim 16 , wherein the etching the portion of the second semiconductor layer comprises forming the second opening with a square profile.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tze-Chung
• Lin Han-Yu
• Lee Fang-Wei
• Lin Li-Te
• Lin Pinyen

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title