FinFETs with strained well regions

Patent metadata

Field	Value
Publication number	US-9601342-B2
Application number	US-201514846020-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Feb 27, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

First claim

What is claimed is:

1. A method comprising: forming a semiconductor fin protruding higher than top surfaces of insulation regions, wherein the insulation regions are on opposite sides of the semiconductor fin; recessing a first sidewall and a second sidewall of the semiconductor fin, wherein the first sidewall and the second sidewall are opposite sidewalls of the semiconductor fin; performing a first epitaxy to grow a semiconductor layer, wherein the semiconductor layer comprises a first sidewall portion contacting the first recessed sidewall of the semiconductor fin, and a second sidewall portion contacting the second recessed sidewall; forming a gate dielectric over the semiconductor fin; forming a gate electrode over the gate dielectric; and epitaxially growing a silicon cap over the semiconductor layer, wherein the silicon cap is underlying the gate dielectric.

2. The method of claim 1 , wherein the recessing the first sidewall and the second sidewall of the semiconductor fin comprises:
forming a photo resist directly over a middle portion of the semiconductor fin; and
etching portions of the semiconductor fin not covered by the photo resist.

3. The method of claim 1 , wherein during the recessing the first sidewall and the second sidewall of the semiconductor fin, a top surface of the semiconductor fin remains not recessed.

4. The method of claim 1 , wherein the first epitaxy comprises:
epitaxially growing a first semiconductor sub-layer, with no p-type and n-type impurity in-situ doped;
epitaxially growing a second semiconductor sub-layer over the first semiconductor sub-layer, with an n-type impurity in-situ doped; and
epitaxially growing a third semiconductor sub-layer over the second semiconductor sub-layer, with no p-type and n-type impurity in-situ doped.

5. The method of claim 1 further comprising forming a source/drain region, wherein the source/drain region contacts both the first sidewall portion and the second sidewall portion of the semiconductor layer, and the source/drain region contacts the recessed semiconductor fin.

6. The method of claim 1 further comprising:
recessing top surfaces of the insulation regions, and a portion of a semiconductor region between the recessed insulation regions forms the semiconductor fin.

7. The method of claim 6 further comprising, before the recessing:
recessing a portion of a substrate between the insulation regions to form a recess;
performing a second epitaxy to grow a first semiconductor region in the recess, wherein the first semiconductor region is relaxed;
performing a third epitaxy to grow a second semiconductor region in the recess, wherein the second semiconductor region is over and contacting the first semiconductor region, and wherein the second semiconductor region has a tensile strain; and
performing a planarization to level top surfaces of the second semiconductor region and the insulation regions.

8. A method comprising:
forming a semiconductor region having a portion over top surfaces of insulation regions, wherein the semiconductor region comprises:
a wide portion with opposite sidewalls contacting edges of the insulation regions, wherein the wide portion has a top surface substantially level with top surfaces of the insulation regions; and
a narrow portion narrower than the wide portion over the wide portion, wherein the wide portion comprises an extension portion laterally extending beyond a respective sidewall of the narrow portion, and the narrow portion has a first bandgap;

epitaxially growing a semiconductor layer contacting a top surface and sidewalls of the narrow portion, wherein the semiconductor layer has a second bandgap greater than the first bandgap; and
forming a gate stack overlapping both the narrow portion and the extension portion of the wide portion.

9. The method of claim 8 , wherein the narrow portion has a tensile stress.

10. The method of claim 8 , wherein the semiconductor layer comprises sidewall portions contacting the sidewalls of the narrow portion, and the method further comprises:
forming a source/drain region contacting the sidewall portions.

11. The method of claim 8 , wherein the epitaxially growing the semiconductor layer comprises:
growing a first sub-layer, wherein substantially no n-type impurity is added into the first sub-layer; and
growing a second sub-layer over the first sub-layer, wherein an n-type impurity is added into the second sub-layer.

12. The method of claim 11 wherein the epitaxially growing the semiconductor layer further comprises:
growing a third sub-layer over the second sub-layer, wherein substantially no n-type impurity is added into the third sub-layer.

13. A method comprising:
recessing a portion of a substrate between two insulation regions to form a recess;
performing a first epitaxy to grow a first semiconductor region in the recess, wherein the first semiconductor region is relaxed;
performing a second epitaxy to grow a second semiconductor region in the recess, wherein the second semiconductor region is over and contacting the first semiconductor region, and wherein the second semiconductor region has a tensile strain;
performing a planarization to level a top surface of the second semiconductor region and the insulation regions;
recessing the insulation regions, wherein a top portion of the second semiconductor region higher than the insulation regions forms a semiconductor fin;
thinning the semiconductor fin; and
performing a third epitaxy to grow a third semiconductor region on a top surface and sidewalls of the semiconductor fin, wherein the second semiconductor region has a conduction band lower than conduction bands of the first and the third semiconductor regions.

14. The method of claim 13 further comprising:
forming a gate dielectric over the third semiconductor region;
forming a gate electrode over the gate dielectric; and
forming a source region and a drain region on opposite sides of the semiconductor fin.

15. The method of claim 14 , wherein after the thinning, a semiconductor region underlying the thinned semiconductor fin has an extension extending beyond sidewalls of the thinned semiconductor fin, and the gate electrode overlaps the extension.

16. The method of claim 13 , wherein the first and the third semiconductor regions comprise silicon germanium, and wherein the second semiconductor region comprises silicon, with a germanium atomic percentage in the second semiconductor region being lower than atomic percentages in the first and the third semiconductor regions.

17. The method of claim 13 , wherein the third epitaxy comprises:
growing a first sub-layer of the third semiconductor region, wherein substantially no n-type impurity is added into the first sub-layer of the third semiconductor region; and
growing a second sub-layer of the third semiconductor region over the first sub-layer of the third semiconductor region, wherein an n-type impurity is added into the second sub-layer of the third semiconductor region.

18. The method of claim 17 , wherein the third epitaxy further comprises:
growing a third sub-layer of the third semiconductor region over the second sub-layer of the third semiconductor region, wherein substantially no n-type impurity is added into the third sub-layer of the third semiconductor region.

19. The method of claim 13 further comprising growing a silicon cap over the third semiconductor region, wherein the silicon cap is substantially free from germanium.

20. The method of claim 1 , wherein

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yi-Jing
• Liu Chi-Wen
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/3438

  Doping during depositing · CPC title