Multiple gate field-effect transistors having oxygen-scavenged gate stack

Patent metadata

Field	Value
Publication number	US-9564489-B2
Application number	US-201514753916-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Jun 29, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric.

First claim

What is claimed is:

1. A method comprising:
forming a silicon cap layer on a semiconductor fin;
forming an interfacial layer over the silicon cap layer;
forming a high-k gate dielectric over the interfacial layer;
forming a scavenging metal layer over the high-k gate dielectric;
performing an anneal on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer; and
depositing a filling metal over the high-k gate dielectric.

2. The method of claim 1 , wherein during the anneal, oxygen is scavenged from a bottom portion of the interfacial layer, and the bottom portion of the interfacial layer is converted into a silicon layer.

3. The method of claim 1 , wherein the forming the silicon cap layer comprises depositing a crystalline silicon layer free from germanium.

4. The method of claim 1 further comprising:
before the anneal, depositing a scavenging-metal-capping layer over the scavenging metal layer, with the scavenging-metal-capping layer and the scavenging metal layer formed of different materials.

5. The method of claim 4 further comprising:
after the anneal, removing the scavenging-metal-capping layer.

6. The method of claim 1 , wherein after the anneal, the interfacial layer comprises:
a top portion intermixed with the high-k gate dielectric to form a compound layer; and
a bottom portion converted into a silicon layer, with the silicon layer and the compound layer in contact with each other.

7. The method of claim 1 , wherein after the anneal, the interfacial layer comprises:
a top portion intermixed with the high-k gate dielectric to form a compound layer;
a bottom portion converted into a silicon layer; and
a middle portion between and in contact with the silicon layer and the compound layer.

8. The method of claim 1 , wherein the anneal comprises a spike anneal.

9. A method comprising:
forming a crystalline silicon cap layer on a silicon germanium fin;
forming a silicon oxide layer over the crystalline silicon cap layer;
forming a high-k gate dielectric over the silicon oxide layer;
forming a scavenging metal layer over the high-k gate dielectric;
scavenging oxygen from a bottom portion of the silicon oxide layer to convert the bottom portion into a silicon layer, with the silicon layer continuously joined with the crystalline silicon cap layer; and
after the scavenging, depositing a filling metal over the high-k gate dielectric.

10. The method of claim 9 further comprising, after the scavenging, removing the scavenging metal layer.

11. The method of claim 9 further comprising:
before the forming the crystalline silicon cap layer, removing a silicon layer from the silicon germanium fin.

12. The method of claim 11 , wherein the removed silicon layer comprises amorphous silicon.

13. The method of claim 9 further comprising:
before the scavenging, depositing a scavenging-metal-capping layer over the scavenging metal layer, with the scavenging-metal-capping layer and the scavenging metal layer formed of different materials.

14. The method of claim 13 further comprising:
after the scavenging, removing the scavenging-metal-capping layer.

15. A method comprising:
forming a dummy gate stack on a middle portion of a silicon germanium fin;
forming source/drain regions on opposite sides of the silicon germanium fin;
forming an inter-layer dielectric over the source/drain regions, with the dummy gate stack in the inter-layer dielectric;
removing the dummy gate stack to form a recess in the inter-layer dielectric;
epitaxially growing a silicon cap layer in the recess, with the silicon cap layer being on the silicon germanium fin;
depositing a silicon oxide layer over and contacting the silicon cap layer;
forming a high-k gate dielectric over the silicon oxide layer;
forming a scavenging metal layer over the high-k gate dielectric, wherein the scavenging metal layer has a first affinity for oxygen higher than a second affinity of a metal in the high-k gate dielectric and a third affinity of silicon;
performing an anneal to scavenge oxygen from at least a bottom portion of the silicon oxide layer to convert the bottom portion into a silicon layer; and
after the anneal, filling a metal into the recess.

16. The method of claim 15 further comprising:
removing an additional silicon layer from the recess, wherein the additional silicon layer is in contact with sidewalls and a top surface of the silicon germanium fin, and the silicon cap layer is grown from the sidewalls and the top surface of the silicon germanium fin.

17. The method of claim 15 further comprising:
after the anneal, removing the scavenging metal layer.

18. The method of claim 15 , wherein the anneal comprises a spike anneal.

19. The method of claim 15 further comprising:
before the anneal, depositing a scavenging-metal-capping layer over the scavenging metal layer, with the scavenging-metal-capping layer and the scavenging metal layer formed of different materials.

20. The method of claim 19 further comprising:
after the anneal, removing the scavenging-metal-capping layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeo Yee-Chia
• Yeh Chih Chieh
• Ko Chih-Hsin
• Wu Cheng-Hsien
• Chen Liang-Yin
• Yu xiong-fei
• Chen Yen-Ming
• Yang Chan-Lon

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/01352

  with sacrificial oxide · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title