Method of spacer patterning to form a target integrated circuit pattern

Patent metadata

Field	Value
Publication number	US-9576814-B2
Application number	US-201514853857-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Dec 19, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

First claim

What is claimed is:

1. A method of forming a target pattern for an integrated circuit, the method comprising:
providing a patterned first spacer layer over a substrate;
forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer; and
forming a patterned material layer over the second spacer layer with a second mask, whereby the patterned material layer and the second spacer layer collectively define a plurality of trenches, and wherein the second spacer layer remains formed over the patterned first spacer layer and on the sidewalls of the patterned first spacer layer after the plurality of trenches are defined.

2. The method of claim 1 , further comprising:
transferring the plurality of trenches to the substrate.

3. The method of claim 1 , further comprising:
etching the second spacer layer through openings of the plurality of trenches to expose the substrate;
etching the substrate through the openings of the plurality of trenches; and
after etching, removing the patterned first spacer layer, the second spacer layer, and the patterned material layer.

4. The method of claim 1 , further comprising:
forming a plurality of lines over the substrate with a first mask;
forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines;
removing at least a portion of the first spacer layer to expose the plurality of lines; and
removing the plurality of lines to provide the patterned first spacer layer.

5. The method of claim 4 , wherein the forming the plurality of lines includes:
forming a resist layer over the substrate; and
patterning the resist layer with the first mask.

6. The method of claim 4 , wherein the forming the plurality of lines includes:
forming a hard mask layer over the substrate;
forming a resist layer over the hard mask layer;
patterning the resist layer with the first mask;
etching the hard mask layer using the patterned resist layer as an etch mask; and
thereafter removing the patterned resist layer.

7. The method of claim 1 , wherein the forming the patterned material layer includes:
forming a first material layer over the second spacer layer;
forming a second material layer over the first material layer and the second spacer layer;
patterning the second material layer with the second mask;
etching the first material layer using the patterned second material layer as an etch mask; and
thereafter removing the patterned second material layer.

8. The method of claim 7 , further comprising:
etching back the first material layer to expose the second spacer layer before forming the second material layer.

9. The method of claim 7 , wherein the patterning the second material layer uses a photolithography process including:
forming a resist layer over the second material layer;
patterning the resist layer with the second mask;
etching the second material layer using the patterned resist layer as an etch mask; and
thereafter removing the patterned resist layer.

10. The method of claim 7 , wherein the etching the first material layer includes a process selectively tuned to remove the first material layer using the patterned second material layer as an etch mask while the second spacer layer remains.

11. The method of claim 4 , wherein the removing at least a portion of the first spacer layer is performed using an anisotropic etching process.

12. The method of claim 4 , wherein the removing the plurality of lines is performed using a plasma etching process.

13. The method of claim 4 , wherein a dimension of at least one of the plurality of trenches is defined, at least in part, by a pattern space of the first mask and a thickness of the first and second spacer layers over the sidewalls of the plurality of lines.

14. A method comprising:
providing a patterned first material over a substrate, the substrate including a plurality of hard mask layers;
depositing a second material to a second thickness over the substrate, over the patterned first material, and onto sidewalls of the patterned first material;
depositing a third material over the second material; and
patterning the second and third materials to form trenches, wherein the second material remains deposited over the patterned first material and on the sidewalls of the patterned first material.

15. The method of claim 14 , further comprising:
forming lines over the substrate;
transferring the lines to at least one hard mask layer of the plurality of hard mask layers;
after transferring the lines to the at least one hard mask layer, depositing a first material to a first thickness over the substrate, over the lines and onto sidewalls of the lines; and
removing the lines to provide the patterned first material.

16. The method of claim 15 , further comprising, before the removing the lines, removing at least a portion of the first material to expose the lines.

17. The method of claim 14 , further comprising, etching the substrate through openings of the trenches.

18. A method of forming a target pattern for an integrated circuit, the method comprising:
decomposing the target pattern to at least a first mask, the first mask having a first mask pattern, and a second mask, the second mask having a second mask pattern, wherein at least a portion of the first mask pattern overlaps with at least a portion of the second mask pattern;
providing a patterned first spacer layer over a substrate;
forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto the sidewalls of the patterned first spacer layer;
forming a first material layer over the second spacer layer; and
patterning the first material layer with the second mask wherein the second spacer layer and the patterned first material layer collectively define a second plurality of features.

19. The method of claim 18 , further comprising:
patterning the substrate with the first mask thereby forming a first plurality of features;
forming a first spacer layer over the substrate, over the first plurality of features, and onto the sidewalls of the first plurality of features;
partially removing the first spacer layer to expose the substrate and the first plurality of features; and
removing the first plurality of features to form the patterned first spacer layer.

20. The method of claim 18 , further comprising:
etching back the first material layer to expose the second spacer layer before patterning the first material layer;
transferring the second plurality of features to the substrate; and
thereafter removing the patterned first material layer and the first and second spacer layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chieh-Han
• Tsai Cheng-Hsiung
• Lee Chung-Ju
• Shieh Ming-Feng
• Liu Ru-Gun
• Shue Shau-Lin
• Bao Tien-I

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title