FinFET devices with unique fin shape and the fabrication thereof

Patent metadata

Field	Value
Publication number	US-9548303-B2
Application number	US-201414207848-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Mar 13, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a dielectric layer disposed over the substrate; and
a fin structure disposed over the dielectric layer;
wherein:
the fin structure contains a semiconductor material;
wherein an interface between the substrate and the dielectric layer is oxidized; and
the dielectric layer disposed below the fin structure includes a lateral recess.

2. The semiconductor device of claim 1 , wherein the semiconductor device includes a p-channel metal-oxide-semiconductor (PMOS) FinFET and an n-channel metal-oxide-semiconductor (NMOS) FinFET, and wherein the fin structure is an NMOS fin structure of the NMOS FinFET.

3. The semiconductor device of claim 2 , wherein the PMOS FinFET includes:
a silicon germanium layer disposed over the substrate;
a silicon layer disposed over the silicon germanium layer; and
a PMOS fin structure disposed over the silicon layer, wherein the PMOS fin structure contains silicon germanium.

4. The semiconductor device of claim 1 , wherein the fin structure includes a [551] surface or a [661] surface.

5. The semiconductor device of claim 1 , wherein the fin structure includes a narrower top portion and a wider bottom portion.

6. The semiconductor device of claim 1 , wherein:
the fin structure contains silicon; and
the dielectric layer includes a silicon germanium oxide layer disposed over the substrate and a silicon oxide layer disposed over the silicon germanium oxide layer.

7. A semiconductor device, comprising:
a p-channel metal-oxide-semiconductor (PMOS) FinFET that includes:
a substrate;
a silicon germanium layer disposed over the substrate;
a silicon layer disposed over the silicon germanium layer; and
a PMOS fin disposed over the silicon layer, wherein the PMOS fin contains silicon germanium; and

an n-channel metal-oxide-semiconductor (NMOS) FinFET that includes:
the substrate;
a silicon germanium oxide layer disposed over the substrate;
a silicon oxide layer disposed over the silicon germanium oxide layer; and
an NMOS fin disposed over the silicon oxide layer, wherein the NMOS fin contains silicon, and wherein the silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction, the concave recess being partially disposed below the NMOS fin.

8. The semiconductor device of claim 7 , wherein at least one of the PMOS fin and the NMOS fin includes a [551] surface or a [661] surface.

9. The semiconductor device of claim 7 , wherein the PMOS fin and the NMOS fin each have bottom portions that are wider than top portions.

10. The semiconductor device of claim 7 , wherein portions of the substrate below the silicon germanium oxide layer is oxidized.

11. A semiconductor device, comprising:
a substrate;
a dielectric layer disposed over the substrate; and
a fin structure disposed over the dielectric layer;
wherein:
the dielectric layer includes a silicon germanium oxide layer disposed over the substrate and a silicon oxide layer disposed over the silicon germanium oxide layer;
the fin structure contains a semiconductor material; and
the dielectric layer disposed below the fin structure includes a lateral recess.

12. The semiconductor device of claim 11 , wherein the semiconductor device includes a p-channel metal-oxide-semiconductor (PMOS) FinFET including:
a silicon germanium layer disposed over the substrate;
a silicon layer disposed over the silicon germanium layer; and
a PMOS fin structure disposed over the silicon layer, wherein the PMOS fin structure contains silicon germanium.

13. The semiconductor device of claim 11 wherein the fin structure includes a [551] surface.

14. The semiconductor device of claim 11 , wherein the fin structure includes a [661] surface.

15. The semiconductor device of claim 11 , wherein the fin structure includes a narrower top portion and a wider bottom portion.

16. The semiconductor device of claim 11 , wherein an interface between the substrate and the dielectric layer is oxidized.

17. The semiconductor device of claim 12 , wherein the semiconductor device includes an n-channel metal-oxide-semiconductor (NMOS) FinFET including:
a silicon germanium oxide layer disposed over the substrate;
a silicon oxide layer disposed over the silicon germanium oxide layer; and
an NMOS fin structure disposed over the silicon oxide layer, wherein the NMOS fin contains silicon, and wherein the silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction, the concave recess being partially disposed below the NMOS fin.

18. The semiconductor device of claim 17 , wherein the PMOS fin and the NMOS fin each have bottom portions that are wider than top portions.

19. The semiconductor device of claim 17 , wherein portions of the substrate below the silicon germanium oxide layer is oxidized.

20. The semiconductor device of claim 1 , wherein the lateral recess has a curved profile in a cross-sectional view.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yi-Jing
• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H01L21/823821

  Electricity · mapped topic

• H01L27/0922 Primary

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic