Method of cutting metal gate

Patent metadata

Field	Value
Publication number	US-9520482-B1
Application number	US-201514940841-A
Country	US
Kind code	B1
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate. The first fin has a first gate region and the second fin has a second gate region. The method also includes forming a metal-gate line over the first and second gate regions. The metal-gate line extends from the first fin to the second fin. The method also includes applying a line-cut to separate the metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming an isolation region within the line cut.

First claim

What is claimed is:

1. A method comprising:
forming a first fin and a second fin on a substrate, the first fin having a first gate region and the second fin having a second gate region;
forming a metal-gate line over the first and second gate regions, wherein the metal-gate line extends from the first fin to the second fin;
applying a line-cut to separate the metal-gate line into a first sub-metal gate line and a second sub-metal gate line; and
forming an isolation region within the line cut.

2. The method of claim 1 , wherein applying the line-cut to separate the metal-gate line into the first sub-metal gate line and the second sub-metal gate line includes:
forming a patterned hard mask over the metal-gate line, wherein the patterned hard mask defines an opening; and
etching the metal-gate line through the opening.

3. The method of claim 1 , wherein forming the isolation region within the line cut includes:
forming a dielectric layer in the line cut; and
recessing the dielectric layer.

4. The method of claim 1 , further comprising:
prior to forming the metal-gate line over the first and second gate regions, forming a dummy gate over the first and second gate regions; and
forming an interlayer dielectric (ILD) layer over the substrate, including over the dummy gate stack.

5. The method of claim 4 , wherein forming the metal-gate line over the first and second gate regions includes:
removing the dummy gate to expose a portion of the first and second gate regions;
depositing a gate dielectric layer over the exposed portions of the first and second gate regions; and
depositing a metal layer over the gate dielectric layer in the first and second gate regions.

6. The method of claim 4 , forming the metal-gate line over the first and second gate regions includes:
removing the dummy gate to expose a portion of the first and second gate regions;
depositing a gate dielectric layer over the exposed portions of the first and second gate regions;
depositing a metal layer over the gate dielectric layer in the first and second gate regions;
recessing a portion of the gate metal layer in the first and second gate regions; and
forming a hard mask over recessed gate metal layer in the first and second gate regions.

7. The method of claim 6 , wherein applying the line-cut to separate the metal-gate line into the first sub-metal gate line and the second sub-metal gate line includes:
forming a patterned hard mask over the hard mask, wherein the patterned hard mask has an opening such that a portion of the gate-metal line aligned within the opening;
etching the hard mask through the opening; and
etching the metal-gate line through the opening.

8. The method of claim 7 , wherein forming the metal-gate line over the first and second gate regions includes forming the metal gate line between sidewall spacers,
wherein the sidewall spacers and a portion of the dielectric layer are exposed within the opening, and
wherein etching the metal-gate line through the opening includes using the exposed sidewall spacers and the portion of the dielectric layer as an etch mask.

9. A method comprising:
forming a plurality of metal gate stacks over a substrate such that the plurality of gate stacks connect to each other to form a metal-gate line, wherein the plurality of metal gate stacks have sidewall spacers disposed along sidewalls of the metal gate stacks;
forming source/drain features in the substrate adjacent the metal gate stacks;
forming an interlayer dielectric (ILD) layer over the metal gate stacks and the source/drain features;
recessing the plurality of metal gate stacks and the sidewall spacers;
forming a hard mask over the recessed plurality of metal gate stacks and the recessed sidewall pacers;
removing a portion of the ILD layer to expose the source/drain features while the hard mask protects the recessed metal gate stacks and the recessed sidewall spacers;
forming a contact metal layer over the exposed source/drain features;
forming a line-cut to cut the metal-gate line into sub-metal-gate lines; and
forming an isolation region within the line cut.

10. The method of claim 9 , wherein forming the plurality of metal gate stacks over the substrate such that the plurality of gate stacks connect to each other to form the metal-gate line includes:
forming a plurality of fins extending from a substrate, each of the fins from the plurality of fins having a source/drain region and a gate region;
forming dummy gate stacks in the each of the gate regions;
removing the dummy gate stacks to expose portions of the fins from the plurality of fins; and
forming the plurality of metal gate stacks over the exposed portions of the fins.

11. The method of claim 9 , wherein recessing the plurality of metal gate stacks and the sidewall spacers includes:
recessing the plurality of metal gate stacks without substantially etching the sidewall spacers;
forming an another hard mask over the recessed plurality of metal gate stacks; and
recessing the sidewall spacers without substantially etching the another hard mask, wherein a top surface of the recessed sidewall spacers is substantially coplanar with a top surface of the hard mask.

12. The method of claim 11 , wherein forming the hard mask over the recessed plurality of metal gates and the recessed sidewall spacers includes forming the hard mask over the another hard mask and the recessed sidewall spacers.

13. The method of claim 9 , wherein forming the line-cut to cut the metal-gate line into sub-metal-gate lines includes:
forming a patterned hard mask over the metal-gate line, wherein the patterned hard mask has an opening; and
etching the metal-gate line through the opening.

14. The method of claim 13 , wherein the recessed sidewall spacers and a portion of the contact metal layer are exposed within the opening, and
wherein etching the metal-gate line through the opening includes using the sidewall spacers and the portion of the contact metal layers as an etch mask.

15. The method of claim 9 , wherein forming the isolation region within the line cut includes;
filling in the line cut with a dielectric layer; and
recessing the dielectric layer.

16. A method comprising:
forming a plurality of fins on a substrate, each of the fins having a gate region;
forming dummy gate stack in each gate region;
forming sidewall spacers along sidewalls of each dummy gate stack;
forming an interlayer dielectric (ILD) layer over the substrate, including beside the dummy gate stacks;
removing the dummy gate stacks to expose portions of the fins in the gate region;
forming metal gate stacks over the exposed portions of the fins, wherein the metal gate stack form a metal-gate line;
recessing the metal gate stacks;
forming a hard mask over the recessed metal gate stacks;
forming a line-cut to cut the metal-gate line into sub-metal-gate lines while the hard mask protects the metal gate stacks; and
forming an isolation region within the line cut.

17. The method of claim 16 , wherein recessing the metal gate stacks includes recessing the metal gate stacks without substantially etching the sidewall spacers and the ILD layer.

18. The method of claim 17 , wherein forming the hard mask over the recessed metal gate stacks includes forming the hard mask over the another hard mask.

19. The method of claim 16 , wherein forming the line-cut to cut the metal-gate line into sub-metal-gate lines includes:
forming a patterned hard mask over the metal-gate line, wherein the patterne

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Po-Chin
• Wang Chih-Hao
• Yang Kai-Chieh
• Hung Shih-Ting
• Wu wei-hao
• Wu Gloria
• Fu Inez
• Su Chia-Wei
• Hsiao Yi-Hsuan

Classifications

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title