Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications

Patent metadata

Field	Value
Publication number	US-2017194430-A1
Application number	US-201615395928-A
Country	US
Kind code	A1
Filing date	Dec 30, 2016
Priority date	Jan 5, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.

First claim

1 . A method of forming nanowire spaces for nanowire structures on a substrate comprising:
performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer; filling the recess with a dielectric material; and removing the dielectric layer extending out of the recess.

2 . The method of claim 1 , further comprising:
forming a liner layer in the recess prior to filling the dielectric material in the recess.

3 . The method of claim 2 , further comprising:
removing the liner layer formed on the first sidewall of the first layer prior to filling the dielectric layer in the recess.

4 . The method of claim 2 , where the liner layer includes more than one layer.

5 . The method of claim 2 , wherein the liner layer is silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride or silicon materials with dopants.

6 . The method of claim 2 , wherein the liner layer is fabricated by an ALD process.

7 . The method of claim 2 , wherein the liner layer has a thickness between about 0.5 nm and about 5 nm.

8 . The method of claim 1 , wherein the first layer of the multi-material layer is an intrinsic silicon layer and the second layer of the multi-material layer is a SiGe layer while the substrate is a silicon substrate.

9 . The method of claim 1 , further comprising:
forming the dielectric layer in the recess as an nanowire spacer in horizontal gate-all-around (hGAA) structures.

10 . The method of claim 1 , wherein the dielectric layer is selected from a group consisting of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbide nitride and doped silicon layer.

11 . The method of claim 1 , wherein filling the recess with the dielectric material comprises:
filling an amorphous carbon from the substrate.

12 . The method of claim 1 , wherein removing the dielectric layer further comprises:
etching the dielectric layer filled over the recess by an isotropic etching process or by an anisotropic etching process.

13 . The method of claim 3 , further comprising:
forming an epi-silicon layer from the first sidewall of the first layer in the multi-material layer.

14 . The method of claim 13 , further comprising:
forming an air gap in the recess.

15 . The method of claim 14 , further comprising:
forming the air gap in the recess as an nanowire air gap spacer in horizontal gate-all-around (hGAA) structures.

16 . The method of claim 3 , further comprising:
performing an oxide treatment process on the liner layer to form an oxidation modification layer predominately formed on the first sidewall of the first layer.

17 . The method of claim 16 , further comprising:
maintaining the liner layer within the recess unchanged from the oxide treatment process.

18 . The method of claim 17 , further comprising:
selectively removing the oxidation modification layer from the first sidewall of the first layer while maintaining the liner layer remained in the recess.

19 . The method of claim 18 , further comprising
forming an epi-silicon layer from the first sidewall of the first layer in the multi-material layer.

20 . The method of claim 19 , further comprising:
forming an air gap in the recess.

Assignees

• Applied Materials Inc

Inventors

• Wood Bingxi Sun
• Ward Michael G
• Sun Shiyu
• Chudzik Michael
• Kim Nam Sung
• Chung Hua
• Huang Yi-Chiau
• Ying Chentsau
• Zhang Ying
• Ni Chi-Nung
• Dong Lin
• Yang Dongqing

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title