FINFETs with wrap-around silicide and method forming the same

Patent metadata

Field	Value
Publication number	US-9608116-B2
Application number	US-201514675215-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Jun 27, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

First claim

What is claimed is:

1. A device comprising:
isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width;
a source/drain region having a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width, and the upper portion of the source/drain region has substantially vertical sidewalls;
a source/drain silicide region with inner sidewalls contacting the vertical sidewalls of the source/drain region; and
a dielectric etch stop layer comprising:
a horizontal portion having a bottom surface contacting a top surface of the isolation regions; and
a vertical portion comprising a bottom end connected to an end of the horizontal portion, wherein the source/drain region comprises a sidewall contacting an inner sidewall of the vertical portion of the dielectric etch stop layer.

2. The device of claim 1 , wherein the vertical portion of the dielectric etch stop layer comprises a top end in contact with a bottom end of the source/drain silicide region.

3. The device of claim 1 further comprising a contact plug having a sidewall comprising:
an upper portion contacting an outer sidewall of the source/drain silicide region; and
a lower portion contacting an outer sidewall of the vertical portion of the dielectric etch stop layer.

4. The device of claim 1 further comprising a silicon germanium oxide region overlapped by the source/drain region and overlapping the substrate strip.

5. The device of claim 4 , wherein the silicon germanium oxide region has a sidewall substantially aligned with a respective sidewall of the substrate strip.

6. The device of claim 1 , wherein the sidewall of the source/drain region is in physical contact with the inner sidewall of the vertical portion of the dielectric etch stop layer.

7. A device comprising:
Shallow Trench Isolation (STI) regions;
a semiconductor strip between opposite portions of the STI regions;
an oxide region overlapping the semiconductor strip; and
a source/drain region overlapping the oxide region, the source/drain region comprising:
a lower portion, wherein respective edges of the semiconductor strip, the oxide region, and the source/drain region are substantially aligned; and
an upper portion over the lower portion, wherein the upper portion comprises substantially vertical sidewalls, and the upper portion extends laterally beyond respective edges of the lower portion.

8. The device of claim 7 further comprising a dielectric etch stop layer comprising portions on opposite sides of the lower portion of the source/drain region, wherein sidewalls of the dielectric etch stop layer are in contact with sidewalls of the lower portion of the source/drain region.

9. The device of claim 8 , wherein the dielectric etch stop layer comprises:
a lower portion contacting a top surface of the STI regions; and
an upper portion forming an L-shape with the lower portion.

10. The device of claim 9 further comprising a contact plug in contact with a sidewall of the lower portion of the dielectric etch stop layer and a top surface of the upper portion of the dielectric etch stop layer.

11. The device of claim 7 , wherein the source/drain region is comprised in a Fin Field-Effect Transistor (FinFET).

12. The device of claim 7 further comprising a silicide region contacting the substantially vertical sidewalls of the source/drain region.

13. The device of claim 12 , wherein no silicide region is in contact with sidewalls of the lower portion of the source/drain region.

14. A device comprising:
Shallow Trench Isolation (STI) regions;
a semiconductor strip between opposite portions of the STI regions;
a source/drain region comprising:
a lower portion overlapping the semiconductor strip; and
an upper portion overlapping the lower portion, wherein the upper portion comprises substantially vertical sidewalls, and the upper portion extends laterally beyond respective edges of the lower portion;

a dielectric etch stop layer comprising portions contacting opposite vertical sidewalls of the lower portion of the source/drain region; and
a silicide region comprising portions contacting the substantially vertical sidewalls of the upper portion of the source/drain region.

15. The device of claim 14 , wherein edges of the semiconductor strip and respective edges of the lower portion of the source/drain region are substantially vertically aligned.

16. The device of claim 14 , wherein the dielectric etch stop layer comprises:
a lower portion contacting a top surface of the STI regions; and
an upper portion forming an L-shape with the lower portion of the dielectric etch stop layer in a cross-sectional view of the dielectric etch stop layer.

17. The device of claim 14 , wherein the portions of the silicide region overlap respective vertical portions of the dielectric etch stop layer.

18. The device of claim 14 , wherein the source/drain region is a part of a Fin Field-Effect Transistor (FinFET).

19. The device of claim 14 , wherein no silicide region is in contact with sidewalls of the lower portion of the source/drain region.

20. The device of claim 1 , wherein the dielectric etch stop layer is in physical contact with the inner sidewall of the vertical portion of the dielectric etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Tsai Ching-Wei
• Liu Chi-Wen
• Wang Chih-Hao
• Leung Ying-Keung

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L29/665

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic