Cut-mask patterning process for fin-like field effect transistor (FinFET) device

Patent metadata

Field	Value
Publication number	US-9236267-B2
Application number	US-201213369818-A
Country	US
Kind code	B2
Filing date	Feb 9, 2012
Priority date	Feb 9, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.

First claim

What is claimed is:

1. A method for patterning a plurality of features in a non-rectangular pattern, the method comprising: providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction; forming a first layer above the surface and above the plurality of elongated protrusions; patterning the first layer with an end cutting mask, the end cutting mask including two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly-adjacent patterns and a portion corresponding to the sub-resolution feature there between; and cutting ends of the elongated protrusions using the pattern on the first layer.

2. The method of claim 1 wherein the first layer is a hardmask layer.

3. The method of claim 1 wherein the first layer is a photoresist layer.

4. The method of claim 1 wherein the plurality of features are fins for fin-like field effect transistor (FinFET) devices.

5. The method of claim 4 wherein the elongated protrusions are silicon nitride spacers.

6. The method of claim 1 wherein the plurality of features are trenches.

7. The method of claim 1 further comprising:
before forming the first layer, forming a second layer above the surface and above the plurality of elongated protrusions;
patterning the second layer with a line cutting mask; and
removing a subset of the elongated protrusions using the pattern on the second layer.

8. A method comprising:
providing a substrate including a surface with a first layer and a second layer;
forming first, second, and third elongated protrusions in a third layer above the first and second layers;
forming a first patterned layer over the three elongated protrusions;
etching the three elongated protrusions to form a first pattern, the first pattern removing a relatively larger portion of the second elongated protrusion, and relatively smaller portions of the first and third elongated protrusions, whereby an area is formed by the larger and smaller portions;
forming a second patterned layer over the first pattern of elongated protrusions, the second pattern including at least two rectangular sub-patterns over the area separated, at least in part, by a sub-resolution feature; and
etching ends of the first and third elongated protrusions that extend in the area.

9. The method of claim 8 , wherein the second patterned layer is a photoresist layer.

10. The method of claim 8 wherein the second pattern layer includes an amorphous silicon hardmask.

11. The method of claim 8 wherein the plurality of elongated protrusions extend in a first direction, and the second pattern layer is configured to make end cuts on the plurality of elongated protrusions in a direction perpendicular to the first direction.

12. The method of claim 8 wherein the second pattern includes three separate rectangular sub-patterns over the area.

13. The method of claim 8 wherein the first layer includes silicon, the second layer includes silicon dioxide, and the elongated protrusions include silicon nitride.

14. The method of claim 13 , where the silicon nitride elongated protrusions in the second pattern are fins of the type used for a fin-type field effect transistor.

15. The method of claim 13 , wherein etching the plurality of elongated protrusions using the second and third patterned layers forms a pattern of trenches in the layer including silicon dioxide.

16. A method for patterning a plurality of features in a non-rectangular pattern, the method comprising:
providing a substrate including a surface with a first layer and a second layer;
forming first, second, and third elongated protrusions in a third layer above the first and second layers;
etching the three elongated protrusions to form a first pattern, the first pattern removing a relatively larger portion of the second elongated protrusion, and relatively smaller portions of the first and third elongated protrusions, whereby an area is formed by the larger and smaller portions;
forming a second patterned layer over the first pattern of elongated protrusions using an end cutting mask, the end cutting mask including at least two rectangular sub-patterns over the area and a sub-resolution feature therebetween; and
etching ends of the first and third elongated protrusions that extend in the area.

17. The method of claim 16 , wherein the end cutting mask is used to produce a patterned photoresist layer over the first pattern of elongated protrusions.

18. The method of claim 16 wherein the end cutting mask includes an amorphous silicon hardmask.

19. The method of claim 16 wherein the plurality of elongated protrusions extend in a first direction, and the end cutting mask is configured to make end cuts on the plurality of elongated protrusions in a direction perpendicular to the first direction.

20. The method of claim 16 wherein the end cutting mask includes three separate rectangular sub-patterns over the area.

Assignees

• De Ho Wei
• Lu Kuei-Liang
• Shieh Ming-Feng
• Chang Ching-Yu
• Taiwan Semiconductor Mfg

Inventors

• De Ho Wei
• Lu Kuei-Liang
• Shieh Ming-Feng
• Chang Ching-Yu

Classifications

• H10P50/696

  Process specially adapted to improve the resolution of the mask · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• G03F1/38 Primary

  Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof · CPC title

• G03F7/70466

  Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475) · CPC title

• H10D86/215

  comprising FinFETs · CPC title