Semiconductor transistor device having backside source/drain contact with a low-k spacer and method of forming the same

Patent metadata

Field	Value
Publication number	US-12464806-B2
Application number	US-202418766991-A
Country	US
Kind code	B2
Filing date	Jul 9, 2024
Priority date	Mar 26, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a channel member; a gate structure disposed over the channel member; a source/drain feature connected to the channel member and adjacent to the gate structure; a source/drain contact disposed below and connected to the source/drain feature; a backside dielectric feature disposed below the channel member; and a first dielectric layer and a second dielectric layer laterally sandwiched between the backside dielectric feature and the source/drain contact, wherein the first dielectric layer includes a low-k dielectric material.

2 . The semiconductor structure of claim 1 , wherein the first dielectric layer includes an air gap.

3 . The semiconductor structure of claim 1 , wherein the first dielectric layer is disposed between the second dielectric layer and the backside dielectric feature, and
wherein the backside dielectric feature interfaces with the gate structure.

4 . The semiconductor structure of claim 1 , further comprising a spacer layer disposed between the source/drain feature and the gate structure,
wherein the spacer layer is disposed directly above the first dielectric layer and a portion of the backside dielectric feature.

5 . The semiconductor structure of claim 1 , wherein the second dielectric layer surrounds the source/drain contact, and
wherein the first dielectric layer surrounds the second dielectric layer.

6 . The semiconductor structure of claim 1 , further comprising:
an insulation layer disposed below the backside dielectric feature, and a backside power rail embedded in the insulation layer and connected to the source/drain contact.

7 . The semiconductor structure of claim 1 , wherein the second dielectric layer is directly below the source/drain feature.

8 . The semiconductor structure of claim 1 , wherein the channel member is a first channel member,
wherein the semiconductor structure further includes a second channel member disposed over the first channel member, and wherein the gate structure wraps around the first channel member and the second channel member.

9 . A semiconductor structure, comprising:
a first dielectric layer; a channel layer disposed over the first dielectric layer; a source/drain feature connected to the channel layer; a metal gate structure disposed over the channel layer; a dielectric spacer disposed between the metal gate structure and the source/drain feature; a second dielectric layer disposed below the dielectric spacer; and a backside contact disposed below the source/drain feature, wherein the second dielectric layer is disposed between the first dielectric layer and the backside contact, and wherein the first dielectric layer interfaces with the metal gate structure.

10 . The semiconductor structure of claim 9 , further comprising a third dielectric layer disposed between the second dielectric layer and the backside contact.

11 . The semiconductor structure of claim 10 , wherein from a top view, the third dielectric layer surrounds the backside contact, the second dielectric layer surrounds the third dielectric layer, and the first dielectric layer surrounds the second dielectric layer.

12 . The semiconductor structure of claim 10 , wherein the third dielectric layer is disposed directly below the source/drain feature.

13 . The semiconductor structure of claim 9 , wherein the second dielectric layer includes an air gap.

14 . A method, comprising:
receiving a workpiece including:
a channel member disposed over a substrate,
a source/drain feature connected to the channel member, and
a sacrificial plug embedded in the substrate and disposed under the source/drain feature;
replacing a bottom portion of the sacrificial plug and a first portion of the substrate adjacent to the bottom portion of the sacrificial plug with a dielectric cap; etching the substrate from a bottom surface of the substrate using the dielectric cap as a mask to form an opening, wherein a second portion of the substrate above the dielectric cap remains after etching the substrate; depositing a backside dielectric layer in the opening; removing the dielectric cap; and selectively removing the second portion of the substrate to form a gap therein.

15 . The method of claim 14 , wherein the dielectric cap covers a bottom surface of the sacrificial plug and is wider than the sacrificial plug in a cross-sectional view.

16 . The method of claim 14 , wherein replacing the bottom portion of the sacrificial plug and the first portion of the substrate adjacent to the bottom portion of the sacrificial plug with the dielectric cap includes:
performing a wet etching process to remove the bottom portion of the sacrificial plug and the first portion of the substrate to form a recess that exposes the second portion of the substrate, wherein the first portion of the substrate is around the bottom portion of the sacrificial plug, and wherein the wet etching process etches the sacrificial plug at a rate greater than etching the substrate.

17 . The method of claim 16 , wherein the forming of the dielectric cap includes:
depositing a dielectric cap layer in the recess; and performing a planarization process to remove excessive dielectric cap below the substrate to form the dielectric cap.

18 . The method of claim 16 , wherein the wet etching process includes implementing ammonium hydroxide and hydrogen peroxide.

19 . The method of claim 14 , wherein the dielectric cap includes silicon nitride, silicon oxide, or silicon oxynitride.

20 . The method of claim 14 , wherein the dielectric cap includes a bottom surface away from the sacrificial plug and a top surface adjacent to the sacrificial plug,
wherein the bottom surface is wider than the top surface.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Po-Yu
• Wu I-Wen
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/076

  in via holes or trenches · CPC title