Method for forming stacked nanowire transistors

Patent metadata

Field	Value
Publication number	US-10032627-B2
Application number	US-201514942546-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A method includes forming a first semiconductor stack using an epitaxial growth process, the first semiconductor stack comprising a first plurality of semiconductor layers alternating with a second plurality of semiconductor layers, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different than the first semiconductor material. The method further includes patterning the first semiconductor stack to form a set of semiconductor stack features, forming isolation features between the semiconductor stack features, removing at least one of the semiconductor stack features, thereby forming at least one trench, and forming, within the trench, a second semiconductor stack using an epitaxial growth process, the second semiconductor stack having different characteristics than the first semiconductor stack.

First claim

What is claimed is:

1. A method comprising:
forming a first semiconductor stack using an epitaxial growth process, the first semiconductor stack comprising a first plurality of semiconductor layers alternating with a second plurality of semiconductor layers, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different than the first semiconductor material;
patterning the first semiconductor stack to form a set of semiconductor stack features;
forming isolation features between the semiconductor stack features;
removing at least one of the semiconductor stack features, thereby forming at least one trench; and
forming, within the trench, a second semiconductor stack using an epitaxial growth process, the second semiconductor stack having different characteristics than the first semiconductor stack.

2. The method of claim 1 , wherein the second semiconductor stack alternates between a third semiconductor material and a fourth semiconductor material.

3. The method of claim 2 , wherein the third semiconductor material and the fourth semiconductor material are different than the first semiconductor material and the second semiconductor material.

4. The method of claim 2 , wherein the third semiconductor material and the fourth semiconductor material are the same as the first semiconductor material and the second semiconductor material, respectively.

5. The method of claim 1 , wherein the first semiconductor stack has a different pitch than the second semiconductor stack.

6. The method of claim 1 , wherein layers of the first semiconductor stack have different thicknesses than layers of the second semiconductor stack.

7. The method of claim 1 , wherein a number of layers of the first semiconductor stack is different than a number of layers of the second semiconductor stack.

8. The method of claim 1 , further comprising, removing the second plurality of semiconductor layers from the first semiconductor stack, thereby forming a series of elongated semiconductor features from the first plurality of semiconductor layers.

9. The method of claim 8 , further comprising, performing an epitaxial growth process to change a size of the elongated semiconductor features.

10. The method of claim 1 , wherein a top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

11. A method comprising:
forming, on a substrate, first semiconductor stack features, each of the first semiconductor stack features comprising a first plurality of semiconductor layers and a second plurality of semiconductor layers that are alternatingly stacked along a first direction perpendicular to a top surface of the substrate, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different from the first semiconductor material;
forming isolation features between the first semiconductor stack features;
removing at least one of the first semiconductor stack features, thereby forming at least one trench; and
forming, on the substrate and within the at least one trench, second semiconductor stack features, each of the second semiconductor stack features comprising a third plurality of semiconductor layers and a fourth plurality of semiconductor layers that are alternatingly stacked along the first direction, the third plurality of semiconductor layers comprising a third semiconductor material and the fourth plurality of semiconductor layers comprising a fourth semiconductor material that is different from the third semiconductor material.

12. The method of claim 11 , further comprising, after the forming of the second semiconductor stack features, etching the isolation features.

13. The method of claim 11 , wherein the first semiconductor stack features comprise different materials from the second semiconductor stack features.

14. The method of claim 11 , wherein the first semiconductor stack features and the second semiconductor stack features are different from each other in at least one of: thickness, pitch, number of layers, or shape.

15. The method of claim 11 , further comprising:
removing the first plurality of semiconductor layers from the first semiconductor stack features; and
forming a gate structure around the second plurality of semiconductor layers.

16. The method of claim 11 , further comprising:
removing the third plurality of semiconductor layers from the second semiconductor stack features; and
forming a gate structure around the fourth plurality of semiconductor layers.

17. The method of claim 11 , wherein top surfaces of the first semiconductor stack features are coplanar with top surfaces of the second semiconductor stack features.

18. A method of forming a semiconductor device, the method comprising:
forming first semiconductor features, each of the first semiconductor features comprising first semiconductor layers and second semiconductor layers that are alternatingly arranged along a first direction perpendicular to a top surface of a substrate, the first semiconductor features comprising a first set of characteristics;
forming isolation features between the first semiconductor features;
removing at least one of the first semiconductor features, thereby forming at least one trench; and
forming, within the at least one trench, at least one second semiconductor feature comprising third semiconductor layers and fourth semiconductor layers that are alternatingly arranged along the first direction, the at least one second semiconductor feature comprising a second set of characteristics that is different from the first set of characteristics.

19. The method of claim 18 , wherein a top surface of a top-most semiconductor layer of the first semiconductor features is coplanar with a top surface of a top-most semiconductor layer of the at least one second semiconductor feature.

20. The method of claim 18 , wherein the first semiconductor features are different from the at least one second semiconductor feature in at least one of: pitch, thickness in respective semiconductor layers, number of semiconductor layers, or shape.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Tung Ying
• Yu Shao-Ming

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10P14/3462 Primary

  Nanowires · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic

• H01L29/1079

  Electricity · mapped topic