Spacers for nanowire-based integrated circuit device and method of fabricating same

Patent metadata

Field	Value
Publication number	US-10475902-B2
Application number	US-201715679681-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	May 26, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Nanowire-based integrated circuit devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a heterostructure over a substrate. A gate structure is formed traversing the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and defines a channel region between the source region and the drain region. A source/drain nanowire release process is performed on the heterostructure to release a nanowire in the source region and the drain region. Nanowire spacers are then formed in the source region and the drain region. The nanowire is disposed between the nanowire spacers. During a gate replacement process, a channel nanowire release process is performed on the heterostructure to release the nanowire in the channel region. Epitaxial source/drain features are formed over the nanowire and the nanowire spacers in the source region and the drain region before the gate replacement process.

First claim

What is claimed is:

1. A method comprising:
forming a heterostructure over a substrate;
forming a gate structure traversing a portion of the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure, a channel region being defined between the source region and the drain region;
performing a source/drain nanowire release process on the heterostructure to release a nanowire in the source region and the drain region;
forming nanowire spacers spanning an entirety of the source region and the drain region, such that the nanowire in the source region and the drain region is disposed between and surrounded by the nanowire spacers; and
during a gate replacement process, performing a channel nanowire release process on the heterostructure to release the nanowire is released in the channel region, wherein the nanowire spacers spanning the entirety of the source region and the drain region function as an etch stop layer during the channel nanowire release process.

2. The method of claim 1 , further comprising, before the gate replacement process, forming epitaxial source/drain features over the nanowire and the nanowire spacers in the source region and the drain region.

3. The method of claim 1 , further comprising performing the source/drain nanowire release process before the gate replacement process.

4. The method of 1 , wherein the forming the nanowire spacers includes:
depositing a nanowire spacer layer over the nanowire, such that the nanowire is surrounded by the nanowire spacer layer; and
patterning the nanowire spacer layer, such that the nanowire spacer layer is removed from sidewalls of the nanowire.

5. The method of claim 4 , wherein the forming the nanowire spacers further includes treating the nanowire spacer layer before the patterning, such that the nanowire spacer layer includes a treated portion and an untreated portion, wherein the treated portion has a different functional characteristic than the untreated portion.

6. The method of claim 5 , wherein the treating include performing an ion implantation process on the nanowire spacer layer.

7. The method of claim 4 , wherein the patterning the nanowire spacer layer includes forming gate spacers adjacent to a dummy gate stack of the gate structure.

8. The method of claim 4 , wherein the forming the nanowire spacer layer includes:
forming a first nanowire spacer layer over the nanowire; and
forming a second nanowire spacer layer over the first nanowire spacer layer.

9. The method of claim 1 , wherein:
the heterostructure includes at least one semiconductor layer pair having a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer, the second semiconductor layer being different than the first semiconductor layer;
the performing the source/drain nanowire release process includes selectively removing the first semiconductor layer from the source region and the drain region, such that the nanowire is formed from the second semiconductor layer in the source region and the drain region; and
the performing the channel nanowire release process includes selectively removing the first semiconductor layer from the channel region, such that the nanowire is formed from the second semiconductor layer in the channel region.

10. The method of claim 9 , wherein the forming nanowire spacers includes forming the nanowire spacers in the channel region where a portion of the first semiconductor layer has been removed during the performing of the source/drain nanowire release process.

11. A method comprising:
forming a semiconductor layer stack over a substrate, wherein the semiconductor layer stack includes at least one first semiconductor layer of a first semiconductor material and at least one second semiconductor layer of a second semiconductor material, the second semiconductor material being different than the first semiconductor material;
forming a gate structure over a channel region of the semiconductor layer stack, wherein the gate structure includes a dummy gate stack;
selectively removing the at least one first semiconductor layer from a source region and a drain region of the semiconductor layer stack;
forming nanowire spacers in the source region and the drain region not underlying the gate structure, such that the at least one second semiconductor layer is disposed between the nanowire spacers in the source region and the drain region not underlying the gate structure;
forming epitaxial source/drain features over the at least one second semiconductor layer and the nanowire spacers in the source region and the drain region not underlying the gate structure;
removing the dummy gate stack to form an opening in the gate structure that exposes the semiconductor layer stack in the channel region;
selectively removing the at least one first semiconductor layer from the channel region of the semiconductor layer stack; and
forming a metal gate stack in the opening of the gate structure.

12. The method of claim 11 , wherein:
the selectively removing the at least one first semiconductor layer from the source region and the drain region of the semiconductor layer stack includes removing a portion of the at least one first semiconductor layer from the channel region;
the forming nanowire spacers includes forming the nanowire spacers in the channel region where the portion of the at least one first semiconductor layer has been removed, such that the nanowire spacers have a portion underlying the gate structure; and
the selectively removing the at least one first semiconductor layer from the channel region of the semiconductor layer stack includes removing a remaining portion of the at least one first semiconductor layer.

13. The method of claim 11 , wherein the forming the nanowire spacers includes:
depositing a nanowire spacer layer over the at least one second semiconductor layer; and
selectively etching the nanowire spacer layer to expose sidewalls of the at least one second semiconductor layer.

14. The method of claim 13 , wherein the depositing the nanowire spacer layer over the at least one second semiconductor layer includes:
depositing a first nanowire spacer layer over the at least one second semiconductor layer in the source region and the drain region; and
depositing a second nanowire spacer layer over the first nanowire spacer layer, wherein the first nanowire spacer layer and the second nanowire spacer layer completely fill a space adjacent to the at least one second semiconductor layer in the source region and the drain region.

15. The method of claim 14 , wherein the selectively etching the nanowire spacer layer includes removing the second nanowire spacer layer from over the gate structure.

16. The method of claim 13 , wherein the forming the nanowire spacers further includes performing an ion implantation process on the nanowire spacer layer before selectively etching the nanowire spacer layer.

17. The method of claim 11 , further comprising forming gate spacers adjacent to the dummy gate stack when forming the nanowire spacers.

18. An integrated circuit device comprising:
a nanowire disposed over a substrate;
a gate structure traversing a portion of the nanowire, such that the gate structure separates a source region and a drain region of the nanowire, wherein a channel region of the nanowire is defined between the source region and the drain region;
a nanowire spacer disposed adjacent to the nanowire, wherein the nanowire spacer spans an entirety of the source region

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Tung Ying
• Yu Shao-Ming

Classifications

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L27/092

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic