Multi-gate device and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-10157799-B2
Application number	US-201815880584-A
Country	US
Kind code	B2
Filing date	Jan 26, 2018
Priority date	Dec 30, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.

First claim

What is claimed is:

1. A device comprising:
a first fin and a second fin disposed over a substrate;
a first gate structure disposed over the first fin, the first gate structure including:
a first gate dielectric layer; and
a first semiconductor layer having a top surface facing away from the substrate, wherein the first gate dielectric layer covers at least a portion of the top surface of the first semiconductor layer;

a first source/drain feature disposed over the first fin, the first source/drain feature including:
the first semiconductor layer;
a second semiconductor layer disposed over the first semiconductor layer; and
a first spacer dielectric layer disposed along a sidewall of the first semiconductor layer without extending to a sidewall of the second semiconductor layer;

a second gate structure disposed over the second fin, the second gate structure including:
a second gate dielectric layer; and
a third semiconductor layer disposed over the second gate dielectric layer; and

a second source/drain feature disposed over the second fin, the second source/drain feature including:
the third semiconductor layer;
a fourth semiconductor layer disposed over the third semiconductor layer; and
a second spacer dielectric layer extending from a top surface of the third semiconductor layer to a bottom surface of the fourth semiconductor layer, the top surface of the third semiconductor layer facing away from the substrate and the bottom surface of the fourth semiconductor layer facing the substrate.

2. The device of claim 1 , wherein the first source/drain feature further includes a conductive layer disposed along the sidewall of the second semiconductor layer.

3. The device of claim 2 , wherein the first spacer dielectric layer extends from another portion of the top surface of the first semiconductor layer to a bottom surface of the second semiconductor layer, the bottom surface of the second semiconductor layer facing the substrate.

4. The device of claim 3 , wherein the conductive layer physically contacts the first spacer dielectric layer extending from the another portion of the top surface of the first semiconductor layer to the bottom surface of the second semiconductor layer.

5. The device of claim 1 , wherein the first gate structure further includes an oxidized semiconductor layer disposed over the first fin and the first semiconductor layer physically contacts the oxidized semiconductor layer.

6. The device of claim 1 , wherein the first gate structure further includes a third gate dielectric layer disposed over the first gate dielectric layer.

7. The device of claim 1 , wherein the second source/drain feature further includes an oxidized semiconductor layer disposed over the second fin and the third semiconductor layer physically contacts the oxidized semiconductor layer.

8. The device of claim 1 , wherein the second source/drain feature further includes a conductive layer extending along sidewall of the third and fourth semiconductor layers.

9. The device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are formed of the same semiconductor material, and
wherein the third semiconductor layer and the fourth semiconductor layer are formed of the same semiconductor material.

10. A device comprising:
a first gate structure disposed over a first fin on a substrate, the first gate structure including:
a first semiconductor layer having a top surface facing away from the substrate and a bottom surface facing the substrate; and
a first gate dielectric layer covering at least a portion of the top surface and at least at a portion of the bottom surface of the first semiconductor layer; and

a first source/drain feature disposed over the first fin, the first source/drain feature including:
the first semiconductor layer;
a second semiconductor layer disposed over the first semiconductor layer;
a first spacer dielectric layer disposed along a sidewall of the first semiconductor layer; and
a first conductive layer disposed along a sidewall of the second semiconductor layer; and

a second gate structure disposed over a second fin on the substrate, the second gate structure including:
a third semiconductor layer having a top surface facing away from the substrate and a bottom surface facing the substrate; and
a second gate dielectric layer covering at least a portion of the top surface and at least at a portion of the bottom surface of the third semiconductor layer; and

a second source/drain feature disposed over the second fin, the second source/drain feature including:
the third semiconductor layer;
a fourth semiconductor layer disposed over the third semiconductor layer;
a second spacer dielectric layer disposed between the third semiconductor layer and the fourth semiconductor layer; and
a second conductive layer disposed along a sidewall of the third semiconductor layer and along a sidewall of the fourth semiconductor layer.

11. The device of claim 10 , wherein the first spacer dielectric layer physically contacts the sidewall of the first semiconductor layer, and
wherein the first conductive layer physically contacts the sidewall of the second semiconductor layer.

12. The device of claim 10 , wherein the second conductive layer physically contacts the sidewall of the third semiconductor layer and the sidewall of the fourth semiconductor layer.

13. The device of claim 10 , further comprising:
a third gate structure extending over a third fin, the third gate structure including:
a fifth semiconductor layer having a top surface facing away from the substrate a bottom surface facing the substrate; and
a third gate dielectric layer covering at least a portion of the top surface and at least at a portion of the bottom surface of the fifth semiconductor layer; and
a fourth gate dielectric layer disposed directly on the third gate dielectric layer and surrounding the fifth semiconductor layer.

14. The device of claim 10 , further comprising a shallow trench isolation structure disposed within the substrate, and
wherein the first spacer dielectric layer physically contacts the shallow trench isolation structure.

15. The device of claim 14 , wherein the first gate dielectric layer physically contacts the shallow trench isolation structure.

16. The device of claim 10 , wherein the second source/drain feature further includes an oxidized semiconductor layer disposed over the second fin, and
wherein the second conductive layer extends from the fourth semiconductor layer to the oxidized semiconductor layer.

17. The device of claim 10 , wherein the a second semiconductor layer has a bottom surface facing the substrate, and
wherein the first spacer dielectric layer physically contacts a first portion of the bottom surface of the second semiconductor layer and the first conductive layer physically contacts a second portion of the bottom surface of the second semiconductor layer.

18. A device comprising:
a first fin element extending from a substrate;
a first gate structure extending over a first channel region of the first fin element, wherein the channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the first gate structure;
a first source/drain region of the first fin element adjacent the first gate structure, wherein the first source/drain region includes:
a first plurality of first semiconductor layers;
a dielectric layer over the first semiconductor layer; and
a second semiconductor layer

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Tsai Ching-Wei
• Diaz Carlos H
• Wang Chih-Hao
• Lien Wai-Yi
• Leung Ying-Keung

Classifications

• H01L27/0924

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L21/823821 Primary

  Electricity · mapped topic