Non-volatile memory device having nanocrystal floating gate and method of fabricating same

Patent metadata

Field	Value
Publication number	US-9899398-B1
Application number	US-201615220171-A
Country	US
Kind code	B1
Filing date	Jul 26, 2016
Priority date	Jul 26, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Methods are disclosed herein for fabricating non-volatile memory devices. An exemplary method forms a heterostructure over a substrate. The heterostructure includes at least one semiconductor layer pair having a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer, the second semiconductor layer being different than the first semiconductor layer. A gate structure having a dummy gate is formed over a portion of the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and a channel region is defined between the source region and the drain region. During a gate replacement process, a nanocrystal floating gate is formed in the channel region from the second semiconductor layer. In some implementations, during the gate replacement process, a nanowire is also formed in the channel region from the first semiconductor layer.

First claim

What is claimed is:

1. A method for fabricating a non-volatile memory device, the method comprising:
forming a heterostructure over a substrate, wherein the heterostructure includes at least one semiconductor layer pair having a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer, the second semiconductor layer being different than the first semiconductor layer;
forming a gate structure that includes a dummy gate over a portion of the heterostructure, the gate structure traversing the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure, a channel region being defined between the source region and the drain region; and
during a gate replacement process for replacing the dummy gate with a control gate over the channel region, forming a nanocrystal floating gate in the channel region from the second semiconductor layer.

2. The method of claim 1 , further comprising forming a nanowire in the channel region from the first semiconductor layer during the gate replacement process.

3. The method of claim 1 , wherein the gate structure further includes gate spacers and sacrificial gate spacers, the method further comprising:
removing the sacrificial gate spacers to form a first opening in the gate structure that exposes a portion of the heterostructure; and
removing the second semiconductor layer from the exposed portion of the heterostructure in the first opening.

4. The method of claim 3 , further comprising:
removing the dummy gate to form a second opening in the gate structure that exposes a remaining portion of the second semiconductor layer in the channel region; and
forming an oxide layer over the remaining portion of the second semiconductor layer.

5. The method of claim 4 , wherein the forming the oxide layer includes:
oxidizing a portion of the remaining portion of the second semiconductor layer and a portion of the first semiconductor layer exposed by the second opening, wherein the second semiconductor layer oxidizes at a higher rate than the first semiconductor layer; and
removing the oxidized portion of the first semiconductor layer.

6. The method of claim 3 , wherein the removing the second semiconductor layer includes performing a selective etching process, wherein the second semiconductor layer has a different etch rate than the first semiconductor layer.

7. The method of claim 1 , wherein the heterostructure includes a first semiconductor layer pair and a second semiconductor layer pair disposed over the first semiconductor layer pair, the first semiconductor layer pair and the second semiconductor layer pair each having the first semiconductor layer and the second semiconductor layer; and
further wherein during the gate replacement process, a first nanocrystal floating gate is formed of the second semiconductor layer in the first semiconductor layer pair, a second nanocrystal floating gate is formed of the second semiconductor layer in the second semiconductor layer pair, and a nanowire is formed of the first semiconductor layer of the second semiconductor layer pair, the nanowire being disposed between the first nanocrystal floating gate and the second nanocrystal floating gate.

8. The method of claim 1 , wherein the gate replacement process includes:
forming a gate dielectric over the first semiconductor layer and the nanocrystal floating gate in the channel region; and
forming a gate electrode over the gate dielectric, wherein the gate includes the gate dielectric and the gate electrode.

9. The method of claim 1 , further comprising forming a control gate contact electrically coupled to the control gate, a source contact electrically coupled to the source, and a drain contact electrically coupled to the drain.

10. The method of claim 1 , further comprising forming epitaxial source/drain features in the source region and the drain region of the heterostructure before the gate replacement process.

11. A method for fabricating a non-volatile memory device, the method comprising:
forming a semiconductor layer stack over a substrate, wherein the semiconductor layer stack includes at least one first semiconductor layer of a first semiconductor material and at least one second semiconductor layer of a second semiconductor material, the second semiconductor material being different than the first semiconductor material;
forming a gate structure over a channel region of the semiconductor layer stack, wherein the gate structure includes a dummy gate stack, sacrificial gate spacers, and gate spacers;
removing the sacrificial gate spacers to form a first opening in the gate structure that exposes a first portion of the semiconductor layer stack in the channel region;
removing a portion of the at least one second semiconductor layer from the exposed first portion of the semiconductor layer stack;
removing the dummy gate stack to form a second opening in the gate structure that exposes a second portion of the semiconductor layer stack in the channel region, wherein the exposed second portion includes at least one second semiconductor layer island;
forming an oxide layer over the at least one second semiconductor layer island; and
forming a metal gate stack in the second opening of the gate structure.

12. The method of claim 11 , wherein the gate structure traverses the semiconductor layer stack in a manner that separates a source region and a drain region of the semiconductor layer stack, the channel region extending horizontally between the source region and the drain region, the method further including forming epitaxial source/drain features over the semiconductor layer stack in the source region and the drain region.

13. The method of claim 11 wherein the forming the oxide layer includes oxidizing portions of the at least one second semiconductor layer island, such that the at least one second semiconductor layer island is surrounded by the oxide layer.

14. The method of claim 13 , wherein the forming the oxide layer further includes:
oxidizing portions of the at least one first semiconductor layer in the exposed second portion of the semiconductor layer stack; and
removing the oxidized portions of the at least one first semiconductor layer.

15. The method of claim 11 , wherein the forming the gate structure includes:
forming the sacrificial gate spacers adjacent to the dummy gate, wherein the sacrificial gate spacers include a first spacer material; and
forming the gate spacers adjacent to the sacrificial gate spacers, wherein the gate spacers include a second spacer material having a different etching rate than the first spacer material.

16. The method of claim 11 , wherein the forming the metal gate stack in the second opening of the gate structure includes:
forming a gate dielectric over the first semiconductor layer in the exposed second portion of the semiconductor layer stack and the oxide layer; and
forming a gate electrode over the gate dielectric.

17. The method of claim 11 , wherein the first opening is defined between the dummy gate stack and the gate spacers, and the second opening is defined between the gate spacers.

18. The method of claim 11 , wherein the semiconductor layer stack includes alternating first semiconductor layers and second semiconductor layers, such that after forming the oxide layer, the channel region includes a nanowire of the first semiconductor material disposed between nanocrystal floating gates of the second semiconductor material.

19. A method for fabric

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Colinge Jean Pierre
• Diaz Carlos H

Classifications

• B82Y30/00

  Nanotechnology for materials or surface science, e.g. nanocomposites · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0673

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L29/4908

  Electricity · mapped topic