Transistor contacts and methods of forming the same
US-2024395871-A1 · Nov 28, 2024 · US
FinFET with bottom SiGe layer in source/drain
US8963258B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963258-B2 |
| Application number | US-201313800817-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
Official abstract text for this publication.
A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A FinFET, comprising: a substrate having a major surface; a fin structure on the substrate, the fin extending from the major surface and having a topmost surface; a source in the fin structure, the source extending below the topmost surface of the fin; a drain in the fin structure, the drain extending below the topmost surface of the fin; a channel in the fin structure between the source and the drain; a gate dielectric layer over the channel; and…
Assignees
Inventors
Classifications
- H10D30/024Primary
Electricity · mapped topic
- H10D30/62Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8963258B2 cover?
- A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D30/024. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).