Multi-gate device and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9818872-B2
Application number	US-201514788161-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method of semiconductor device fabrication is described that includes forming a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition. The second epitaxial layer is removed from the source/drain region of the fin to form a gap. The gap is filled with a dielectric material. Another epitaxial material is formed on at least two surfaces of the first epitaxial layer to form a source/drain feature.

First claim

What is claimed is:

1. A method of semiconductor device fabrication, comprising:
forming a first fin extending from a substrate, the first fin having a source/drain region and a channel region, wherein the first fin includes a first epitaxial layer having a first composition and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second composition;
forming a second fin extending from the substrate and having a source/drain region and a channel region, wherein the second fin includes the first epitaxial layer and the second epitaxial layer;
oxidizing the second epitaxial layer of the second fin, while a hard mask layer protects the first fin;
removing the second epitaxial layer from the source/drain region of the first fin to form a gap;
filling the gap with a dielectric material; and
while the dielectric material is filled within the gap, growing a first source/drain epitaxial material on at least two surfaces of the first epitaxial layer to form a first source/drain feature on the first fin; and
growing a second source/drain epitaxial material on the first epitaxial layer of the second fin, to form a second source/drain, and wherein the second source/drain epitaxial material are adjacent the oxidized second epitaxial layer.

2. The method of claim 1 , further comprising:
prior to forming the first epitaxial layer, forming a third epitaxial layer underlying the first epitaxial layer;
oxidizing the third epitaxial layer to form an oxidized third epitaxial layer;
wherein the oxidized third epitaxial layer underlies a gate on the channel region and the first source/drain feature.

3. The method of claim 1 , further comprising:
removing the second epitaxial layer from the channel region of the first fin to from another gap; and
forming a gate structure on the first epitaxial layer in the channel region, wherein at least a portion of the gate structure is formed in the another gap.

4. The method of claim 1 , further comprising:
prior to forming the first fin, performing an anti-punch through (APT) ion implantation into the substrate; and
after performing the APT ion implantation and prior to forming the first fin, depositing the first epitaxial layer over the substrate and the second epitaxial layer over the first epitaxial layer.

5. The method of claim 1 , further comprising:
forming the first epitaxial layer by growing a silicon layer; and
forming the second epitaxial layer by growing a silicon germanium layer directly on the silicon layer.

6. The method of claim 1 , wherein the first epitaxial layer has a first oxidation rate, and wherein the second epitaxial layer has a second oxidation rate greater than the first oxidation rate.

7. The method of claim 1 , wherein the oxidized second epitaxial layer is greater in thickness than the second epitaxial layer thereby providing a top surface of the first epitaxial layer in the channel region below a top surface of the first epitaxial layer in the source/drain region of the second fin.

8. The method of claim 1 , further comprising:
forming a gate structure on the first fin, wherein the gate structure is disposed over top, bottom and opposing lateral sides of the first epitaxial layer in the channel region.

9. The method of claim 8 , further comprising:
forming a high-k gate dielectric of the gate structure over the top, bottom and opposing lateral sides of the first epitaxial layer in the channel region.

10. The method of claim 1 , wherein a channel of a first type of device is formed in the fin and a channel of a second type of device is formed in the another fin, the first type being one of an NFET and a PFET and the second type being the other one of the NFET and the PFET.

11. A method of fabricating a multi-gate device, the method comprising:
forming an bottom epitaxial layer;
growing an epitaxial layer stack including first, second, and third epitaxial layers over the bottom epitaxial layer;
oxidizing the bottom epitaxial layer to form an oxide layer;
patterning the epitaxial layer stack to form a fin element;
forming a dummy gate structure over the fin element;
transforming the second epitaxial layer in a first region and a second region of the fin to a dielectric layer, wherein the first and second regions are interposed by a third region of the fin, wherein the third region underlies the dummy gate structure, wherein a thickness of the oxide layer is greater than the thickness of the dielectric material;

removing the dummy gate structure after transforming the second epitaxial layer, thereby forming a trench; and
forming a metal gate structure in the trench, wherein the metal gate structure is disposed on multiple sides of each of the first and third epitaxial layers.

12. The method of claim 11 , wherein the transforming includes oxidizing the second epitaxial layer in the first region.

13. The method of claim 11 , wherein the transforming includes:
removing the second epitaxial layer in the first region to form a gap; and
filling the gap with a dielectric material.

14. The method of claim 11 , further comprising:
after removing the dummy gate structure, removing the second epitaxial layer from the third region of the fin to form a gap in the third region.

15. The method of claim 14 , wherein a high-k dielectric layer of the metal gate structure is disposed in the gap in the third region.

16. The method of claim 13 ,
wherein the filling the gap with a dielectric material includes depositing a spacer layer and etching back the spacer layer, wherein the etching back removes the spacer layer from a top surface of the dummy gate structure and sidewalls of the first epitaxial layer, wherein the spacer layer continues to fill the gap after the etching back.

17. The method of claim 16 ,
wherein the etching back includes removing the spacer layer from a top surface of the third epitaxial layer.

18. The method of claim 16 , wherein the spacer layer defines sidewalls of the trench.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Tsai Ching-Wei
• Diaz Carlos H
• Wang Chih-Hao
• Lien Wai-Yi
• Leung Ying-Keung

Classifications

• H01L29/66439

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/775

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic