Structure of S/D contact and method of making same

Patent metadata

Field	Value
Publication number	US-10199502-B2
Application number	US-201414460438-A
Country	US
Kind code	B2
Filing date	Aug 15, 2014
Priority date	Aug 15, 2014
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first fin feature over a substrate;
a second fin feature over the substrate extending parallel to the first fin feature;
a first stack of semiconductor layers over the first fin feature, wherein each layer of the first stack of semiconductor layers does not contact a remainder of the first stack of semiconductor layers, wherein the first stack of semiconductor layers includes a first semiconductor layer and a second semiconductor layer;
a second stack of semiconductor layers over the second fin feature, wherein each layer of the second stack of semiconductor layers does not contact a remainder of the second stack of semiconductor layers;
a semiconductor oxide layer interposed between the first fin feature and the first stack of semiconductor layers, wherein a surface of the semiconductor oxide layer physically contacts the first fin feature and an opposite surface of the semiconductor oxide layer physically contacts a bottom layer of the first stack of semiconductor layers; and
a conductive material layer surrounding each semiconductor layer of the first and second stacks of semiconductor layers and filling in spaces between the semiconductor layers, the conductive material layer having the same material composition extending from the first semiconductor layer to the second semiconductor layer such that the conductive material layer physically contacts the first and second semiconductor layers, wherein a region of the conductive material layer between topmost layers of the first and second stacks of semiconductor layers includes:
a first portion of substantially uniform width;
a second portion disposed on the first portion having a width that decreases in a direction away from the substrate; and
a third portion disposed on the second portion having a width that increases in the direction away from the substrate.

2. The device of claim 1 , further comprising an isolation region disposed between the first fin feature and the second fin feature.

3. The device of claim 2 , wherein a top surface of the semiconductor oxide layer is below a top surface of the isolation region.

4. The device of claim 1 , wherein the conductive material layer includes a metal layer.

5. The device of claim 1 , wherein both of the first stack of semiconductor layers and the semiconductor oxide layer are vertically aligned to the first fin feature.

6. The device of claim 1 , further comprising:
the conductive material layer filling in spaces between two stacks of semiconductor layers.

7. The device of claim 1 , wherein the semiconductor oxide layer has a same width as a width of the first fin feature.

8. A semiconductor device comprising:
a fin feature over a substrate;
a source and drain (S/D) feature over the fin feature, the S/D feature including:
a stack of semiconductor layers, wherein each of the semiconductor layers does not contact each other, wherein the stack of semiconductor layer includes a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer includes:
a lower portion having side surfaces that are substantially vertical;
a middle portion having side surfaces that taper outwards from the side surfaces of the lower portion; and
an upper portion having side surfaces that taper inwards from the side surfaces of the middle portion;

a semiconductor oxide layer interposed between the fin feature and the S/D feature, wherein a surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers; and
a metal layer encircling each of the semiconductor layers of the S/D feature and filling in spaces between each of two semiconductor layers, the metal layer having the same material composition extending from the first semiconductor layer to the second semiconductor layer such that the metal layer physically contacts the first and second semiconductor layers.

9. The device of claim 8 , wherein both of the S/D feature and the semiconductor oxide layer are vertically aligned to each other.

10. The device of claim 8 , further comprising:
a conductive material layer filling in spaces between two S/D features.

11. The device of claim 8 , wherein the semiconductor oxide layer has a same width as a width of the second semiconductor layer of the fin feature.

12. The device of claim 8 , further comprising an isolation region disposed between two adjacent fin features.

13. The device of claim 12 , wherein a top surface of the semiconductor oxide layer is same or below a top surface of the isolation region.

14. A semiconductor device comprising:
a substrate;
a fin feature formed on the substrate;
semiconductor layers stacked on the fin feature, wherein:
the semiconductor layers are separated from each other by a conductive material layer;
the semiconductor layers includes a first semiconductor layer and a second semiconductor layer;
the conductive material layer has the same material composition extending from the first semiconductor layer to the second semiconductor layer such that the conductive material layer physically contacts the first and second semiconductor layers;
the first semiconductor layer has a first cross-sectional shape profile that includes:
a first portion having substantially uniform width;
a second portion disposed on the first portion and tapering outward in a direction away from the substrate; and
a third portion disposed on the second portion and tapering inward in the direction away from the substrate; and

the second semiconductor layer has a second cross-sectional shape profile that is different than the first cross-sectional shape profile; and

a semiconductor oxide layer interposed between the fin feature and the semiconductor layers, wherein a surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the semiconductor layers.

15. The device of claim 14 , wherein the conductive material layer includes a metal layer.

16. The device of claim 14 , wherein the conductive material layer surrounds each of the semiconductor layers.

17. The device of claim 14 , wherein the semiconductor layers are included in a source and drain feature.

18. The device of claim 14 , further comprising a first dielectric isolation feature on a first side of the fin feature and a second dielectric isolation feature on a second side of the fin feature, the second side of the fin feature being opposite the first side, and
wherein the semiconductor oxide layer extends from the first dielectric isolation feature to the second dielectric isolation feature.

19. The device of claim 8 , further comprising a first dielectric isolation feature on a first side of the fin feature and a second dielectric isolation feature on a second side of the fin feature, the second side of the fin feature being opposite the first side, and
wherein the semiconductor oxide layer extends from the first dielectric isolation feature to the second dielectric isolation feature.

20. The device of claim 8 , wherein the semiconductor oxide layer includes germanium.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien
• Lee Tung Ying
• Fan Chun-Hsiang

Classifications

• H01L29/7851

  Electricity · mapped topic

• H01L2029/7858

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L29/7853 Primary

  Electricity · mapped topic