Threshold voltage adjustment for a gate-all-around semiconductor structure

Patent metadata

Field	Value
Publication number	US-10290546-B2
Application number	US-201715666715-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Nov 29, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

First claim

What is claimed is:

1. A method, comprising:
providing a semiconductor structure that includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, the first and second semiconductor layers having different material compositions;
forming a dummy gate stack over an uppermost first semiconductor layer;
performing a first etching process to remove portions of the second semiconductor layers that are not disposed below the dummy gate stack, thereby forming a plurality of voids, wherein the first etching process has an etching selectivity between the first semiconductor layers and the second semiconductor layers;
thereafter performing a second etching process to enlarge the voids; and
epitaxially growing a third semiconductor layer in the enlarged voids.

2. The method of claim 1 , wherein the etching selectivity between the first semiconductor layers and the second semiconductor layers is configured such that the first etching process removes the portions of the second semiconductor layers without removing the first semiconductor layers.

3. The method of claim 1 , wherein the second etching process is performed to enlarge a horizontal dimension of each of the voids.

4. The method of claim 1 , wherein:
the first semiconductor layers each include a silicon layer; and
the second semiconductor layers each include a silicon germanium layer.

5. The method of claim 1 , further comprising: replacing the dummy gate stack with a gate structure having a high-k gate dielectric and a metal gate electrode.

6. The method of claim 5 , wherein the replacing the dummy gate stack comprises replacing portions of the second semiconductor layers disposed below the dummy gate stack with a plurality of gate structures having a high-k gate dielectric and a metal gate electrode.

7. The method of claim 6 , wherein for each of the gate structures that replaces the portions of the second semiconductor layers, the high-k gate dielectric circumferentially wraps around the metal gate electrode.

8. The method of claim 1 , wherein the forming the dummy gate stack comprises forming a plurality of dummy gate stacks in a first region and a second region of the semiconductor structure, and wherein the first etching process and the second etching process are performed such that voids in the first region and voids in the second region have different horizontal dimensions.

9. The method of claim 8 , wherein the second etching process is performed in the first region but not in the second region.

10. The method of claim 8 , wherein:
the first region is a standard threshold voltage (SVt) region; and
the second region is a high threshold voltage (HVt) region.

11. A method, comprising:
providing a semiconductor structure that includes a plurality of first semiconductor layers and a plurality of second semiconductor layers, the first and second semiconductor layers having different material compositions and are alternatingly disposed with respect to each other in a vertical direction;
forming a plurality of dummy gate stacks over an uppermost first semiconductor layer;
removing portions of the second semiconductor layers in a first region of the semiconductor structure, thereby forming a plurality of first spaces in place of the removed portions of the second semiconductor layers in the first region;
extending the first spaces horizontally via a lateral etching process; and
thereafter removing portions of the second semiconductor layers in a second region of the semiconductor structure, thereby forming a plurality of second spaces in place of the removed portions of the second semiconductor layers in the second region, wherein remaining portions of the second semiconductor layers in the first region have different horizontal dimensions than remaining portions of the second semiconductor layers in the second region.

12. The method of claim 11 , further comprising: performing a gate replacement process to replace the dummy gate stacks and the remaining portions of the second semiconductor layers in both the first region and the second region with gate structures that each include a high-k gate dielectric and a metal gate electrode.

13. The method of claim 11 , further comprising: growing a plurality of third semiconductor layers in the plurality of first spaces and the plurality of second spaces.

14. A method, comprising:
forming a plurality of first semiconductor layers and a plurality of second semiconductor layers, the first semiconductor layers interleaving with, and having a different material composition than, the second semiconductor layers;
performing a first etching process to form a plurality of voids in the second semiconductor layers but not in the first semiconductor layers; and
after the first etching process is performed, performing a second etching process to increase at least a lateral dimension of each of the voids, wherein the second etching process and the first etching process have different etching parameters; and
after the second etching process is performed, performing an epitaxial growth process to form a third semiconductor layers in each of the voids.

15. The method of claim 14 , wherein:
the first semiconductor layers each include a silicon layer; and
the second semiconductor layers each include a silicon germanium layer.

16. The method of claim 14 , further comprising:
before the first etching process is performed, forming one or more dummy gates over an uppermost one of the first semiconductor layers; and
after the second etching process is performed, replacing each of the one or more dummy gates and portions of the second semiconductor layers with a gate structure having a high-k gate dielectric and a metal gate electrode, wherein the high-k gate dielectric circumferentially wraps around the metal gate electrode.

17. The method of claim 16 , wherein the one or more dummy gates are formed in both a standard threshold voltage (SVt) region and a high threshold voltage (HVt) region.

18. The method of claim 17 , wherein the second etching process is performed in the SVt region but not in the HVt region.

19. The method of claim 17 , wherein the voids formed in the SVt region have different sizes than the voids formed in the HVt region.

20. The method of claim 14 , wherein the second etching process has a smaller vertical bias voltage than the first etching process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Hung-Li
• Huang Szu-Wei
• Wei huan-sheng
• Ho Jon-Hsu
• Yeh Chih Chieh
• Hsieh Wen-Hsing
• Wu Chung-Cheng
• Yeo Yee-Chia

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title