Conductive structures and methods of fabrication thereof

Patent metadata

Field	Value
Publication number	US-12362273-B2
Application number	US-202217745890-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	Dec 30, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Embodiments of the present disclosure relate to methods of fabricating conductive features to prevent metal extrusion. Particularly, the conductive feature includes a control layer to reduce grain size of a metal containing layer, thus obtaining a robust structure to decrease extrusion defects. In some embodiments, the control layer is formed between a barrier layer and the conductive feature. In some embodiments, the control layer is formed by adding a control element, such as oxygen, to an upper portion of the barrier layer.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming an interconnect structure over a substrate, wherein the interconnect structure comprises a top conductive layer;
depositing a barrier layer on the top conductive layer, wherein the barrier layer comprises a first element;
forming a control layer on the barrier layer; and
depositing a conductive pad layer on the control layer, wherein the conductive pad layer comprises a second element; and
patterning the conductive pad layer, the control layer, and the barrier layer to form a conductive pad structure;
wherein the barrier layer includes a first concentration peak of the first element, the conductive pad layer includes a second concentration peak of the second element, the control layer comprises the first element and a third element, a third concentration peak of the third element is located within the control layer, and the third concentration peak is lower than the first concentration peak and the second concentration peak.

2. The method of claim 1 , wherein forming the control layer comprises adding the third element into an upper portion of the barrier layer.

3. The method of claim 2 , wherein the third element is oxygen, and adding the third element comprises exposing the barrier layer to air.

4. The method of claim 3 , wherein the barrier layer has a first thickness, the control layer has a second thickness, and a ratio of the second thickness over the first thickness is in a range between 0.01 and 0.5.

5. The method of claim 1 , wherein depositing the barrier layer comprises depositing nitride layer of the first element, and the first element is tantalum, titanium, or tungsten, the second element is aluminum, copper, or tantalum, and the third element is oxygen.

6. A method, comprising:
forming an interconnect structure on a substrate, wherein the interconnect structure comprises a top conductive layer; and
forming a conductive pad structure on the interconnect structure, wherein the conductive pad structure comprises:
a barrier layer on the top conductive layer, wherein the barrier layer comprises a first element;
a control layer on the barrier layer; and
a conductive pad on the control layer, wherein the conductive pad comprises a second element,
wherein the control layer comprises the first element and a third element, a first concentration peak of the first element is located in the barrier layer, a second concentration peak of the second element is located in the conductive pad, a third concentration peak of the third element is located within the control layer, and the third concentration peak is lower than the first concentration peak and the second concentration peak.

7. The method of claim 6 , wherein the first element is tantalum, titanium, or tungsten, the second element is aluminum, copper, or tantalum, and the third element is oxygen.

8. The method of claim 7 , wherein the control layer further comprises nitrogen.

9. The method of claim 6 , wherein the barrier layer has a first thickness, the control layer has a second thickness, and a ratio of the second thickness over the first thickness is in a range between 0.01 and 0.5.

10. The method of claim 9 , wherein the first thickness is in a range between 10 nm and 200 nm.

11. The method of claim 10 , wherein the control layer has a composition MxNyOz, M denotes the first element, N denotes nitrogen, O denotes oxygen, x, y, z are numerals, and z is greater than x.

12. The method of claim 11 , wherein the third concentration peak is in a range between 35% and 70%.

13. The method of claim 9 , wherein the conductive pad includes an interface layer in contact with the control layer, and a grain size in the interface layer is in a range between 10 nm and 400 nm.

14. A method, comprising:
providing a substrate having a plurality of electronic components;
depositing a first dielectric layer over the plurality of electronic components;
forming a first conductive feature embedded in the first dielectric layer;
forming a barrier layer on the first conductive feature, wherein the barrier layer comprises a first metal element and nitrogen, and has a first thickness;
forming a control layer on the barrier layer, wherein the control layer has a second thickness, and a ratio of the second thickness over the first thickness is in a range between 0.01 and 0.5; and
forming a second conductive feature on the control layer, wherein the second conductive feature comprises a second metal element,
wherein the control layer comprises the first metal element, nitrogen, and a third element, and the third element has a higher concentration than the first metal element in the control layer.

15. The method of claim 14 , further comprising:
depositing a second dielectric layer in contact with the barrier layer; and
forming an opening in the second dielectric layer, wherein the second conductive feature formed disposed in the opening in the second dielectric layer.

16. The method of claim 15 , wherein the second dielectric layer is an intermetal dielectric (IMD) layer in an interconnect structure on the substrate.

17. The method of claim 15 , wherein the second dielectric layer is a passivation layer over an interconnect structure on the substrate, and the first conductive feature is a top conductive feature of the interconnect structure.

18. The method of claim 14 , wherein the second conductive feature includes an interface layer in contact the control layer and a bulk layer in contact with the interface layer, the interface layer has a first grain size in a range between 10 nm and 400 nm, and the bulk layer has a second grain size in a range between 300 nm and 1200 nm.

19. The method of claim 18 , wherein the second conductive feature has a third thickness, the interface layer has a fourth thickness, and a ratio of the fourth thickness over the third thickness is in a range between 0.01 and 0.1.

20. The method of claim 15 , wherein a first concentration peak of the first metal element is located in the barrier layer, a second concentration peak of the second metal element is located in the second conductive feature, a third concentration peak of the third element is located within the control layer, and the third concentration peak is lower than the first concentration peak and the second concentration peak.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nian Jun-Nan
• Liang Yao-Hsiang
• Tsai Jian-Shin
• Chung Ming-Ching
• Liao Chun-I

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title