Self aligned contact scheme

Patent metadata

Field	Value
Publication number	US-9859386-B2
Application number	US-201715407112-A
Country	US
Kind code	B2
Filing date	Jan 16, 2017
Priority date	Apr 4, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

First claim

What is claimed is:

1. A method comprising:
forming a first gate over a substrate;
forming a first dielectric layer over the substrate and surrounding the first gate;
forming a first hard mask layer over the first gate;
forming a second hard mask layer over the first hard mask layer;
planarizing the second hard mask layer to have a top surface level with a top surface of the first dielectric layer;
forming a second dielectric layer over the first gate and the first dielectric layer;
etching a first opening through the second dielectric layer and the first dielectric layer to expose a portion of the substrate;
filling the first opening with a conductive material; and
recessing the second hard mask layer, the conductive material, and the second dielectric layer to level top surfaces of the first hard mask layer, the conductive material, and the first dielectric layer, the recessed conductive material forming a first conductive contact.

2. The method of claim 1 further comprising:
first gate spacers on opposing sidewalls of the first gate and the first hard mask layer.

3. The method of claim 2 , wherein the second hard mask layer is on top surfaces of the first gate spacers.

4. The method of claim 1 , wherein the second hard mask layer comprises a metal nitride or a metal oxide.

5. The method of claim 4 , wherein the second hard mask layer comprises TiO, HfO, AlO, ZrO, ZrN, or a combination thereof.

6. The method of claim 1 , wherein forming the first gate over the substrate comprises:
forming a first dummy gate over the substrate, the first dummy gate comprising a first dummy gate dielectric on the substrate and a first dummy gate electrode on the first dummy gate dielectric;
forming first gate spacers on opposing sidewalls of the first dummy gate;
forming source/drain regions in the substrate using the first dummy gate and first gate spacers as a mask;
forming a first etch stop layer over the substrate, the first dummy gate, and the first gate spacers;
forming the first dielectric layer over the first etch stop layer;
planarizing the first dielectric layer to expose a portion of the first dummy gate; and
replacing the first dummy gate with the first gate.

7. The method of claim 1 further comprising:
recessing the first gate to have a top surface below the top surface the first dielectric layer, the first hard mask layer being formed on the recessed top surface of the first gate; and
recessing the first hard mask layer to have a top surface below the top surface of the first dielectric layer, the second hard mask layer being formed on the recessed top surface of the first hard mask layer.

8. The method of claim 1 further comprising:
after recessing the second hard mask layer, the conductive material, and the second dielectric layer, forming a third dielectric layer over the first hard mask layer and the first dielectric layer; and
forming a second conductive contact through the third dielectric layer to the first conductive contact.

9. The method of claim 8 , wherein a bottom surface of the second conductive contact contacts a top surface of the first hard mask layer and a top surface of the first conductive contact.

10. A method comprising:
forming a first metal gate over a substrate, the first metal gate having first gate spacers on opposing sidewalls of the first metal gate;
forming a first dielectric layer over the substrate and adjacent the first metal gate;
recessing the first metal gate to have a top surface below a top surface of a the first dielectric layer;
forming a first hard mask layer on the recessed top surface of the first metal gate;
recessing the first hard mask layer and the first gate spacers to have top surfaces below the top surface of the first dielectric layer; and
forming a second hard mask layer on the recessed top surfaces of the first hard mask layer and the first gate spacers.

11. The method of claim 10 further comprising:
planarizing the second hard mask layer to have a top surface level with the top surface of the first dielectric layer.

12. The method of claim 10 , wherein the second hard mask layer comprises a metal nitride or a metal oxide.

13. The method of claim 10 , wherein the first metal gate comprises a high-k gate dielectric layer on the substrate and along inner sidewalls of the first gate spacers and a metal gate electrode on the high-k gate dielectric layer.

14. The method of claim 10 further comprising:
forming a second dielectric layer over the second hard mask layer and first hard mask layer;
etching a first opening through the second and first dielectric layers to expose a portion of the substrate, at least a portion of the second hard mask layer overlying the first metal gate being exposed in the first opening;
filling the first opening with a conductive material; and
removing the second dielectric layer and the second hard mask layer and the portions of the conductive material and second and first dielectric layer above the first hard mask layer to form a first conductive contact in the first dielectric layer.

15. The method of claim 14 , wherein an entire top surface of the second hard mask layer overlying the first metal gate is exposed in the first opening.

16. The method of claim 14 further comprising:
after removing the second dielectric layer and the second hard mask layer and the portions of the conductive material and second and first dielectric layer above the first hard mask layer, forming a third dielectric layer over the first hard mask layer and the first dielectric layer; and
forming a second conductive contact through the third dielectric layer to the first conductive contact.

17. A method comprising:
forming a first gate and a second gate over a substrate, the first gate and the second gate each having gate spacers on opposing sidewalls of the respective gates;
forming a first dielectric layer over the substrate and surrounding the first gate and the second gate;
forming a first hard mask layer and a second hard mask layer over the first gate and the second gate;
forming a second dielectric layer over the second hard mask layer and the first dielectric layer;
etching a first opening through the second dielectric layer and the first dielectric layer to expose a portion of the substrate adjacent the first gate, at least a portion of the gate spacers on the sidewall of the first gate exposed in the first opening; and
etching a second opening through the second dielectric layer and the first dielectric layer to expose a portion of the substrate adjacent the second gate, the gate spacers on the sidewall of the second gate not being exposed in the second opening.

18. The method of claim 17 further comprising:
recessing the first gate and the second gate to have top surfaces below a top surface the first dielectric layer, the first hard mask layer being formed on the recessed top surfaces of the first gate and the second gate; and
recessing the first hard mask layer to have a top surface below the top surface of the first dielectric layer, the second hard mask layer being formed on the recessed top surfaces of the first hard mask layer.

19. The method of claim 18 further comprising:
filling the first opening and second opening with a conductive material; and
removing the second dielectric layer and the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first opening and a second co

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Tsai-Jung
• Hsu Kuang-Yuan
• Jeng Pei-Ren

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H01L29/665

  Electricity · mapped topic

• H01L21/76897

  Electricity · mapped topic