Self aligned contact scheme

Patent metadata

Field	Value
Publication number	US-9548366-B1
Application number	US-201615090341-A
Country	US
Kind code	B1
Filing date	Apr 4, 2016
Priority date	Apr 4, 2016
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

First claim

What is claimed is:

1. A method comprising:
forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls of the first gate;
forming a first hard mask layer over the first gate;
forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer;
forming a first dielectric layer adjacent and over the first gate;
etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening;
filling the first opening with a conductive material; and
removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

2. The method of claim 1 , wherein the second hard mask layer comprises a metal nitride or a metal oxide.

3. The method of claim 2 , wherein the second hard mask layer comprises TiO, HfO, AlO, ZrO, ZrN, or a combination thereof.

4. The method of claim 1 , wherein the first gate spacers extend along opposing sidewalls of the first hard mask layer.

5. The method of claim 4 , wherein the second hard mask layer is on top surfaces of the first gate spacers.

6. The method of claim 1 , wherein the first gate comprises a high-k gate dielectric layer on the substrate and along inner sidewalls of the first gate spacers and a metal gate electrode on the high-k gate dielectric layer.

7. The method of claim 1 , wherein forming the first gate over the substrate comprises:
forming a first dummy gate over the substrate, the first dummy gate comprising a first dummy gate dielectric on the substrate and a first dummy gate electrode on the first dummy gate dielectric;
forming the first gate spacers on opposing sidewalls of the first dummy gate;
forming source/drain regions in the substrate using the first dummy gate and first gate spacers as a mask;
forming a first etch stop layer over the substrate, first dummy gate, and the first gate spacers;
forming a first portion of the first dielectric layer over the first etch stop layer;
planarizing the first portion of the first dielectric layer to expose a portion of the first dummy gate; and
replacing the first dummy gate with the first gate.

8. The method of claim 1 further comprising:
recessing the first gate to have a top surface below a top surface of a first portion of the first dielectric layer, the first hard mask layer being formed on the recessed top surface of the first gate;
recessing the first hard mask layer to have a top surface below the top surface of the first portion of the first dielectric layer, the second hard mask layer being formed on the recessed top surface of the first hard mask layer; and
planarizing the second hard mask layer to have a top surface coplanar with the top surface of the first portion of the first dielectric layer.

9. The method of claim 8 further comprising:
forming a second portion of the first dielectric layer over the planarized second hard mask layer and first portion of the first dielectric layer, the first opening extending through the second portion and the first portion of the first dielectric layer;
after the removing the second hard mask layer, forming a second etch stop layer over the first hard mask layer and the first portion of the first dielectric layer;
forming a second dielectric layer over the second etch stop layer; and
forming a second conductive contact through the second dielectric layer and the second etch stop layer to the first conductive contact.

10. The method of claim 9 , wherein a bottom surface of the second conductive contact contacts a top surface of the first hard mask layer and a top surface of the first conductive contact.

11. A method comprising:
forming a first metal gate and a second metal gate over a substrate, the first metal gate and the second metal gate each having gate spacers on opposing sidewalls of the respective metal gates;
forming a first dielectric layer over the substrate and adjacent the first and second metal gates;
recessing the first metal gate and the second metal gate to have top surfaces below a top surface of a the first dielectric layer;
forming a first hard mask layer on the recessed top surfaces of the first metal gate and the second metal gate;
recessing the first hard mask layer to have top surfaces below the top surface of the first dielectric layer;
forming a second hard mask layer on the recessed top surfaces of the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer; and
planarizing the second hard mask layer to have a top surface coplanar with the top surface of the first dielectric layer.

12. The method of claim 11 further comprising:
forming a second dielectric layer over the planarized second hard mask layer and first hard mask layer;
etching a first opening through the second and first dielectric layers to expose a portion of the substrate, at least a portion of the second hard mask layer overlying the first metal gate being exposed in the first opening;
filling the first opening with a conductive material; and
removing the second hard mask layer and the portions of the conductive material and second and first dielectric layer above the first hard mask layer to form a first conductive contact in the first dielectric layer.

13. The method of claim 12 , wherein an entire top surface of the second hard mask layer overlying the first metal gate is exposed in the first opening.

14. The method of claim 12 further comprising:
etching a second opening through the second dielectric layer, the second hard mask layer, and the first hard mask layer to expose a portion of the second metal gate; and
filling the second opening with the conductive material, the removing the second hard mask layer and the portions of the conductive material and second and first dielectric layer above the first hard mask layer forming a second conductive contact in the first hard mask layer.

15. The method of claim 11 , wherein the second hard mask layer comprises a metal nitride or a metal oxide.

16. The method of claim 11 , wherein the first metal gate comprises a high-k gate dielectric layer on the substrate and along inner sidewalls of the gate spacers and a metal gate electrode on the high-k gate dielectric layer.

17. The method of claim 11 , wherein forming the first metal gate and the second metal gate over the substrate comprises:
forming a first dummy gate and a second dummy gate over the substrate;
forming the gate spacers on opposing sidewalls of the first dummy gate and the second dummy gate;
forming a first etch stop layer over the substrate, first dummy gate, the second dummy gate, and the gate spacers;
forming the first dielectric layer over the first etch stop layer;
planarizing the first dielectric layer to expose portions of the first dummy gate and the second dummy gate; and
replacing the first dummy gate with the first metal gate and the second dummy gate with the second metal gate.

18. A structure comprising:
a first gate stack on a substrate, the first gate stack comprising a first high-k gate dielectric layer and a first metal gate electrode;
a first hard mask layer on the first gate stack;
a first set of gate spacers on opposing sidewalls of the first gate stack and the first hard mask layer;
a first etch

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Tsai-Jung
• Hsu Kuang-Yuan
• Jeng Pei-Ren

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic