Semiconductor devices having a tsv, a front-side bumping pad, and a back-side bumping pad

Patent metadata

Field	Value
Publication number	US-2016155686-A1
Application number	US-201514953857-A
Country	US
Kind code	A1
Filing date	Nov 30, 2015
Priority date	Dec 1, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a first interlayer insulating layer disposed on a front-side of the substrate; a through silicon via (TSV) structure passing through the first interlayer insulating layer and the substrate, wherein the TSV structure has a bottom end protruding from a back-side of the substrate; a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate; and a back-side bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure, wherein the bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

2 . The semiconductor device of claim 1 , wherein the TSV structure comprises:
a TSV plug; a TSV barrier layer surrounding side surfaces of the TSV plug; and a TSV liner surrounding side surfaces of the TSV barrier layer, wherein the TSV plug has a top end and a bottom end which are not surrounded by the TSV barrier layer and the TSV liner and exposed by the TSV barrier layer and the TSV liner.

3 . The semiconductor device of claim 2 , wherein the back-side bumping pad comprises:
a back-side pad electrode; a back-side pad seed layer surrounding a bottom surface and side surfaces of the back-side pad electrode; and a back-side pad barrier layer surrounding a bottom surface and side surfaces of the back-side pad seed layer, wherein the back-side pad barrier layer is in contact with the TSV plug.

4 . The semiconductor device of claim 3 , wherein the back-side insulating layer has portions which remain as a spacer between the back-side bumping pad and the TSV structure.

5 . The semiconductor device of claim 1 , further comprising:
a TSV connection circuit disposed on the first interlayer insulating layer; a second interlayer insulating layer covering the TSV connection circuit; and a front-side bumping pad disposed on the second interlayer insulating layer, wherein the TSV connection circuit comprises: a TSV connection pad disposed on the first interlayer insulating layer to be in contact with the TSV structure, and a TSV connection via disposed on the TSV connection pad, and the TSV connection via protrudes from a surface of the second interlayer insulating layer into the front-side bumping pad.

6 . The semiconductor device of claim 5 , wherein the front-side bumping pad comprises:
a front-side pad electrode; a front-side pad seed layer surrounding a bottom surface and side surfaces of the front-side pad electrode; and a front-side pad barrier layer surrounding a bottom surface and side surfaces of the front-side pad seed layer, wherein the front-side pad barrier layer is in contact with the TSV connection via.

7 . The semiconductor device of claim 1 , further comprising:
a MOS transistor disposed on the front-side of the substrate; and an inner wire and an inner via disposed on the first interlayer insulating layer, wherein the inner via is electrically connected with the substrate or the MOS transistor.

8 . The semiconductor device of claim 1 , wherein the back-side insulating layer comprises silicon oxide and the back-side passivation layer comprises silicon nitride.

9 . The semiconductor device of claim 8 , wherein the back-side insulating layer is in contact with side surfaces of the TSV structure, and the back-side passivation layer is not in contact with the side surfaces of the TSV structure.

10 . The semiconductor device of claim 1 , further comprising:
a back-side blocking layer disposed between the back-side insulating layer and the back-side passivation layer and be in contact with side surfaces of the back-side bumping pad, wherein the back-side blocking layer comprises silicon carbonitride.

11 . The semiconductor device of claim 10 , further comprising:
a back-side stopper layer disposed between the back-side insulating layer and the back-side blocking layer to be in contact with the side surfaces of the back-side bumping pad, wherein the back-side stopper layer comprises silicon nitride.

12 . A semiconductor device comprising:
a substrate; a MOS transistor disposed on a front-side of the substrate; a first interlayer insulating layer covering the MOS transistor; a through silicon via (TSV) structure passing through the first interlayer insulating layer and the substrate; a TSV connection circuit disposed on the first interlayer insulating layer to be electrically connected with a top end of the TSV structure; a front-side bumping pad disposed on the front-side of the substrate to be electrically connected with the TSV connection circuit; and a back-side bumping pad disposed on a back-side of the substrate and connected with the TSV structure, wherein a bottom end of the TSV structure protrudes into the back-side bumping pad.

13 . The semiconductor device of claim 12 , wherein the TSV connection circuit comprises:
a TSV pad disposed on the first interlayer insulating layer to be in contact with the top end of the TSV structure; a lower TSV connection via on the TSV pad; a TSV connection wire on the lower TSV connection via; and an upper TSV connection via on the TSV connection wire.

14 . The semiconductor device of claim 13 , wherein the upper TSV connection via comprises:
a TSV connection via plug; and a TSV via barrier layer surrounding a bottom surface and side surfaces of the TSV connection via plug and being in contact with the TSV connection wire, wherein the TSV connection via plug has a top end which protrudes into the front-side bumping pad.

15 . The semiconductor device of claim 12 , further comprising:
an inner circuit disposed on the first interlayer insulating layer; a second interlayer insulating layer covering the inner circuit and the TSV connection circuit; and a front-side insulating layer and a front-side passivation layer disposed on the second interlayer insulating layer, wherein the front-side insulating layer and the front-side passivation layer surround side surfaces of the front-side bumping pad.

16 . A semiconductor device comprising:
a substrate; a first interlayer insulating layer disposed on a front-side of the substrate; a through silicon via (TSV) structure passing through the first interlayer insulating layer and the substrate; a TSV connection circuit disposed on the first interlayer insulating layer to be electrically connected with a top end of the TSV structure; a second interlayer insulating layer disposed on the first interlayer insulating layer to cover the TSV connection circuit; a front-side bumping pad disposed on the second interlayer insulating layer to be electrically connected with the TSV connection circuit; a back-side bumping pad disposed on a back-side of the substrate and connected with a bottom end of the TSV structure; and a back-side blocking layer disposed on the back-side of the substrate and in contact with side surfaces of the back-side bumping pad, wherein the bottom end of the TSV structure protrudes into the back-side bumping pad, and the back-side blocking layer comprises silicon carbonitride.

17 . The semiconductor device of claim 16 , wherein the TSV connection circuit comprises:
a TSV pad disposed on the first interlayer insulating layer to be in contact with the top end of the TSV structure; and a TSV connection via in contact with the front-side bumping pad, wherein the TSV conne

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Jin
• Park Byunglyul
• Park Jisoon
• An Jinho

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title