Wrap-around contact

Patent metadata

Field	Value
Publication number	US-9443769-B2
Application number	US-201414257809-A
Country	US
Kind code	B2
Filing date	Apr 21, 2014
Priority date	Apr 21, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces.

First claim

What is claimed is:

1. A method comprising:
forming a first fin structure and a second fin structure on a substrate, an isolation region being disposed between the first fin structure and the second fin structure, the first fin structure comprising a first epitaxial region extending above the isolation region, the second fin structure comprising a second epitaxial region extending above the isolation region, each of the first epitaxial region and the second epitaxial region having a widest mid-region between an upper-surface and an under-surface;
forming a dual-layer etch stop over the first fin structure and the second fin structure, the dual-layer etch stop comprising a first sub-layer and a second sub-layer, the first sub-layer being along the upper-surface of the first epitaxial region, the under-surface of the first epitaxial region, the upper-surface of the second epitaxial region, the under-surface of the second epitaxial region, and the isolation region, the second sub-layer being over the first sub-layer and along the upper-surface of the first epitaxial region and the upper-surface of the second epitaxial region, the second sub-layer merging together proximate the widest mid-region of the first epitaxial region and the widest mid-region of the second epitaxial region;
removing at least portions of the dual-layer etch stop from the upper-surface and the under-surface of the first epitaxial region and from the upper-surface and the under-surface of the second epitaxial region;
forming a first dielectric layer on at least portions of the upper-surface and the under-surface of the first epitaxial region and on the upper-surface and the under-surface of the second epitaxial region;
forming a metal layer on the first dielectric layer on at least the upper-surface of the first epitaxial region and the upper-surface of the second epitaxial region; and
forming a barrier layer on the metal layer and along the under-surface of the first epitaxial region and the under-surface of the second epitaxial region.

2. The method of claim 1 , wherein after the removing the at least portions of the dual-layer etch stop, at least a portion of the first sub-layer remains along the under-surface of the first epitaxial region and the under-surface of the second epitaxial region.

3. The method of claim 1 further comprising forming a second dielectric layer over the dual-layer etch stop before removing the at least portions of the dual-layer etch stop, a void being formed between the first fin structure and the second fin structure.

4. The method of claim 1 further comprising reacting at least a portion of the metal layer with the first epitaxial region and the second epitaxial region to form a metal-semiconductor compound.

5. The method of claim 1 , wherein the forming the dual-layer etch stop comprises:
depositing the first sub-layer using an atomic layer deposition (ALD) process; and
depositing the second sub-layer using a plasma enhanced chemical vapor deposition (PECVD) process.

6. The method of claim 5 , wherein the first sub-layer is silicon carbon nitride (SiCN), and the second sub-layer is silicon nitride (SiN).

7. The method of claim 1 , wherein:
the forming the first dielectric layer comprises using an atomic layer deposition (ALD) process;
the forming the metal layer comprises using a radio frequency physical vapor deposition (RF-PVD) process; and
the forming the barrier layer comprises using a chemical vapor deposition (CVD) process.

8. The method of claim 7 , wherein the first dielectric layer is titanium oxide (TiO 2 ), the metal layer is titanium (Ti), and the barrier layer is titanium nitride (TiN).

9. The method of claim 1 further comprising forming a buffer dielectric layer on the first fin structure and the second fin structure, the dual-layer etch stop being formed on the buffer dielectric layer.

10. A method comprising:
forming a neighboring pair of fin structures on a substrate, the fin structures each comprising an epitaxial region extending above an isolation region disposed between the fin structures;
conformally forming a first etch stop layer over the fin structures and the isolation region;
forming a second etch stop layer on the first etch stop layer and on upper surfaces of the epitaxial regions, the second etch stop layer merging between the fin structures proximate mid-regions of the epitaxial regions of the fin structures, the merging of the second etch stop layer forming an enclosed void between the fin structures;
forming a dielectric layer over the second etch stop layer;
removing at least a portion of the second etch stop layer;
removing at least a portion of the first etch stop layer from the upper surfaces of the epitaxial regions and from under-surfaces of the epitaxial regions; and
forming a contact structure on the fin structures, the contact structure comprising a metal oxide layer, a metal layer, and a metal nitride layer, the metal oxide layer being on the upper surfaces and under-surfaces of the epitaxial regions, the metal layer being on the metal oxide layer and along at least the upper surfaces of the epitaxial regions, and the metal nitride layer being on the metal layer and along the upper surfaces and under-surfaces of the epitaxial regions.

11. The method of claim 10 , wherein after the removing at least the portion of the first etch stop layer, at least a portion of the first etch stop layer remains along the under-surfaces of the epitaxial regions.

12. The method of claim 10 further comprising reacting at least a portion of the metal layer with the epitaxial regions to form a metal-semiconductor compound.

13. The method of claim 10 , wherein the forming first etch stop layer comprises using an atomic layer deposition (ALD) process, the first etch stop layer being silicon carbon nitride (SiCN), and the forming second etch stop layer comprises using a plasma enhanced chemical vapor deposition (PECVD) process, the second etch stop layer being silicon nitride (SiN).

14. The method of claim 10 , wherein the metal oxide layer is formed using an atomic layer deposition (ALD) process and is titanium oxide (TiO 2 ), the metal layer is formed using a radio frequency physical vapor deposition (RF-PVD) process and is titanium (Ti), and the metal nitride layer is formed using a chemical vapor deposition (CVD) process and is titanium nitride (TiN).

15. The method of claim 10 further comprising forming a buffer oxide layer on the fin structures, the first etch stop layer being formed on the buffer oxide layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sung-Li
• Chen Neng-Kuo
• Shih Ding-Kang
• Chang Meng-Chun
• Lin Yi-An
• Huang Gin-Chen
• Hsu Chen-Feng
• Lin Hau-Yu
• Ko Chih-Hsin
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title