Semiconductor device

Patent metadata

Field	Value
Publication number	US-12113109-B2
Application number	US-202117313638-A
Country	US
Kind code	B2
Filing date	May 6, 2021
Priority date	Jun 16, 2020
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a first active region and a second active region adjacent to the first active region in a first direction, the first active region being one of PMOSFET and NMOSFET regions, the second active region being the other one of the PMOSFET and NMOSFET regions;
a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region;
a gate electrode extended in the first direction to cross the first and second active patterns;
a first source/drain pattern on the first active pattern and a second source/drain pattern on the second active pattern, wherein each of the first source/drain pattern and the second source/drain pattern is adjacent to a side of the gate electrode;
an interlayer insulating layer on the gate electrode;
a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern; and
a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact,
wherein upper surfaces of the buffer layer, the first and second active contacts, and the interlayer insulating layer all lie in a same plane, and
wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

2. The semiconductor device of claim 1 , wherein the buffer layer extends in a second direction which crosses the first direction, between the first active region and the second active region.

3. The semiconductor device of claim 1 , wherein a width of the buffer layer in the first direction gradually decreases with decreasing distance from the substrate.

4. The semiconductor device of claim 1 , further comprising:
a third active contact spaced apart from the first active contact and the second active contact in a second direction to connect the first source/drain pattern and the second source/drain pattern.

5. The semiconductor device of claim 4 , wherein the third active contact comprises:
a first body portion on the first source/drain pattern, a second body portion on the second source/drain pattern, a first protruding portion, a second protruding portion, and a recessed portion between the first body portion and the second body portion,
wherein the first protruding portion, the second protruding portion, and the recessed portion are provided on the device isolation layer between the first active region and the second active region, and
the recessed portion includes a portion of the third active contact having a bottom recessed in a direction away from the device isolation layer.

6. The semiconductor device of claim 5 , wherein the first protruding portion is provided between the first body portion and the recessed portion,
the second protruding portion is provided between the second body portion and the recessed portion,
a bottom surface of the recessed portion is higher than bottom surfaces of the first protruding portion and the second protruding portion, and
the bottom surface of the recessed portion is lower than a bottom surface of the first body portion.

7. The semiconductor device of claim 5 , wherein a level of a bottom surface of the first protruding portion is different from a level of a bottom surface of the second protruding portion,
a largest width of the first protruding portion in the first direction is different from a largest width of the second protruding portion in the first direction, and
a level of a bottom surface of the first body portion is lower than a level of a bottom surface of the second body portion.

8. The semiconductor device of claim 5 , wherein the first protruding portion extends from the first body portion towards the device isolation layer along an inclined side surface of the first source/drain pattern, and
the second protruding portion extends from the second body portion towards the device isolation layer along an inclined side surface of the second source/drain pattern.

9. The semiconductor device of claim 5 , wherein the first body portion is electrically connected to a top surface of the first source/drain pattern, and
the first protruding portion is electrically connected to an inclined side surface of the first source/drain pattern.

10. The semiconductor device of claim 5 , further comprising:
a gate contact on the first active region and connecting the gate electrode,
wherein the third active contact further comprises an upper insulating pattern formed in an upper portion of the first body portion and adjacent to the gate contact.

11. A semiconductor device, comprising:
a first active region, a second active region and a third active region respectively arranged across a substrate in a first direction, the first active region and the second active region having different conductivity types, and the second active region and the third active regions having a same conductivity type;
a device isolation layer on the substrate and defining a first active pattern on the first active region, a second active pattern on the second active region, and a third active pattern on the third active region;
a gate electrode extending in the first direction to cross the first, second, and third active patterns;
a first source/drain pattern, a second source/drain pattern, and a third source/drain pattern respectively provided on the first active pattern, the second active pattern and the third active pattern, wherein each of the first source/drain pattern, the second source/drain pattern, and the third source/drain pattern is adjacent to a side of the gate electrode;
an interlayer insulating layer on the gate electrode;
a first active contact electrically connected to the first source/drain pattern and the second source/drain pattern;
a second active contact electrically connected to the third source/drain pattern; and
a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact,
wherein upper surfaces of the buffer layer, the first and second active contacts, and the interlayer insulating layer all lie in a same plane, and
wherein the buffer layer comprises a material having an etch selectivity with respect to the interlayer insulating layer.

12. The semiconductor device of claim 11 , wherein the buffer layer comprises a first buffer layer extending in a second direction within the interlayer insulating layer and aligned above a region extending between the first active region and the second active region, and a second buffer layer extending in the second direction within the interlayer insulating layer and aligned above a region extending between the second active region and the third active region.

13. The semiconductor device of claim 11 , wherein a length of the second active contact in the first direction is less than about half of a length of the first active contact in the first direction.

14. The semiconductor device of claim 11 , wherein the first active contact comprises:
a first body portion on the first active region;
a second body portion on the second active region; and
a first protruding portion, a second protruding portion, and a recessed portion between the first and second body portions,
wherein the first protruding portion, the second protruding portion, and the recessed portion are provided on the device isolation layer between t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sungmin
• Park Juhun
• Bae Deokhan
• Um Myungyoon
• Lee Yuri
• Lee Inyeal
• Jung Yoonyoung
• Hong Sooyeon

Classifications

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0186 Primary

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D30/6219 Primary

  characterised by the source or drain electrodes · CPC title