Semiconductor device, semiconductor device layout, and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9613953-B2
Application number	US-201514666444-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	Mar 24, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A layout of a semiconductor device is stored on a non-transitory computer-readable medium. The layout includes an active area region extending in a first direction, a gate electrode extending in a second direction and crossing the active area region, and a dummy gate extending in the second direction. The dummy gate is adjacent the gate electrode. The dummy gate is a dielectric dummy gate.

First claim

What is claimed is:

1. A layout of a semiconductor device, the layout stored on a non-transitory computer-readable medium and comprising:
an active area region extending in a first direction;
a gate electrode extending in a second direction, and crossing the active area region; and
a dummy gate extending in the second direction, the dummy gate adjacent the gate electrode,
wherein the dummy gate is a dielectric dummy gate.

2. The layout of claim 1 , further comprising:
a transistor comprising the active area region and the gate electrode,
wherein the transistor has a source or drain region formed over the active area region between the gate electrode and the dummy gate.

3. The layout of claim 1 , further comprising:
spacers extending in the second direction over sidewalls of the gate electrode and the dummy gate,
wherein the dummy gate comprises at least one dielectric material filled in a space between the corresponding spacers.

4. The layout of claim 3 , further comprising:
a dummy gate region comprising the dummy gate and the corresponding spacers,
wherein the active area region terminates in the dummy gate region.

5. The layout of claim 1 , further comprising:
a further gate electrode extending in the second direction, and crossing the active area region,
wherein
the gate electrode is between the further gate electrode and the dummy gate, and
a distance between the gate electrode and the dummy gate is equal to a distance between the gate electrode and the further gate electrode.

6. The layout of claim 1 , further comprising:
a further dummy gate extending in the second direction, and adjacent the dummy gate,
wherein the dummy gate is between the further dummy gate and the gate electrode.

7. The layout of claim 6 , wherein
the further dummy gate is a dielectric dummy gate.

8. The layout of claim 6 , wherein
the further dummy gate is a conductive dummy gate.

9. The layout of claim 6 , wherein
a distance between the gate electrode and the dummy gate is equal to a distance between the dummy gate and the further dummy gate.

10. The layout of claim 6 , further comprising:
a further gate electrode extending in the second direction, and adjacent the further dummy gate; and
a further active area region extending in the first direction, and crossing the further gate electrode,
wherein
the active area region and the further active area region are aligned and spaced from each other in the first direction, and
the further dummy gate is between the further gate electrode and the dummy gate.

11. A semiconductor device, comprising:
a substrate;
first and second active area regions over the substrate and extending in a first direction;
first and second gate electrodes over the substrate and extending in a second direction, the first and second gate electrodes crossing the corresponding first and second active area regions;
an isolation structure over the substrate; and
a dummy gate over the isolation structure and extending in the second direction,
wherein
the dummy gate is a dielectric dummy gate, and
the first active area region and the second active area region are aligned in the first direction, and spaced from each other by the dielectric dummy gate.

12. The semiconductor device of claim 11 , wherein
the first active area region and the second active area region have opposing ends facing each other in the first direction, and
the dielectric dummy gate is between and in contact with the opposing ends of the first and second active area regions.

13. The semiconductor device of claim 11 , further comprising:
a plurality of spacers along sides of the corresponding first and second gate electrodes and dielectric dummy gate,
wherein
the first active area region and the second active area region have opposing ends facing each other in the first direction, and
the dielectric dummy gate comprises at least one dielectric material filled in
a first space between the corresponding spacers, and
a second space below the first space and between the opposing ends of the first and second active area regions.

14. The semiconductor device of claim 11 , wherein
a width of the first or second gate electrode in the first direction is equal to a width of the dielectric dummy gate in the first direction.

15. The semiconductor device of claim 11 , wherein
a distance between the first gate electrode and the dielectric dummy gate is equal to a distance between the dielectric dummy gate and the second gate electrode.

16. The semiconductor device of claim 11 , further comprising:
a first circuit comprising the first active area region and the first gate electrode; and
a second circuit comprising the second active area region and the second gate electrode,
wherein
the first and second circuits share a common edge corresponding to the dielectric dummy gate, and
at least one of the first circuit or the second circuits has
a further edge opposite to the common edge in the first direction,
a further dielectric dummy gate corresponding to the further edge, and
spacers along sides of the further dielectric dummy gate, wherein the corresponding active area region terminates in a dielectric dummy gate region including the further dielectric dummy gate and the corresponding spacers.

17. The semiconductor device of claim 16 , further comprising:
another dummy gate adjacent the further dielectric dummy gate in the first direction.

18. A semiconductor device, comprising:
a substrate;
a fin structure over the substrate, wherein the fin structure extends in a first direction parallel to a top surface of the substrate;
an isolation structure over the substrate;
a gate electrode over the fin structure, wherein the gate electrode comprises a conductive material, and the gate electrode extends in a second direction perpendicular to the first direction; and
a gate structure over the isolation structure and the fin structure, wherein the gate structure is free of conductive materials, and the gate structure extends in the second direction.

19. The semiconductor device of claim 18 , wherein the gate structure comprises:
a gate dielectric material; and
a dummy dielectric material, wherein the gate dielectric material is between the dummy dielectric material and the fin structure.

20. The semiconductor device of claim 18 , wherein the gate structure comprises:
spacers defining an area between the spacers; and
a dummy dielectric material filling the area, wherein the dummy dielectric material directly contacts the fin structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L27/088 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic