Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10141307-B2
Application number	US-201715631821-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Mar 3, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a first fin structure and a second fin structure, both disposed over the substrate, the first and second fin structures extending in a first direction in plan view, upper portions of the first and second fin structures being exposed from the isolation insulating layer;
a first gate structure disposed over parts of the first and second fin structures, the first gate structure extending in a second direction crossing the first direction;
first fin sidewall spacers covering a lower portion of the exposed first fin structure, and second fin sidewall spacers covering a lower portion of the exposed second fin structure; and
a source/drain structure formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation insulating layer, and wrapping side surfaces and a top surface of each of the exposed first and second fin structures, wherein:
a void is formed between the source/drain structure and the isolation insulating layer,
one of the first fin sidewall spacers and one of the second fin sidewall spacers are disposed in the void, and
an entirety of side surface of the one of the first fin sidewall spacers and an entirety of side surface of the one of the second fin sidewall spacers are exposed in the void.

2. The semiconductor device of claim 1 , further comprising:
an interlayer dielectric layer disposed over the first gate structure and the source/drain structure;
a silicide layer formed on the source/drain structure; and
a contact plug formed in the interlayer dielectric layer and connected to the silicide layer.

3. The semiconductor device of claim 2 , wherein the silicide layer is not formed on a part of an upper surface of the source/drain structure, which is not in contact with the contact plug.

4. The semiconductor device of claim 2 , further comprising an insulating layer disposed between the source/drain structure and the interlayer dielectric layer.

5. The semiconductor device of claim 4 , wherein the insulating layer is not formed in the void.

6. The semiconductor device of claim 2 , further comprising a second gate structure disposed over parts of the first and second fin structures, wherein:
the second gate structure extends in the second direction crossing the first direction and is arranged in parallel with the first gate structure in the first direction in plan view, and
the void is formed in an area defined by the first and second fin structures and the first and second gate structures in plan view.

7. The semiconductor device of claim 1 , further comprising a second gate structure disposed over parts of the first and second fin structures, wherein:
the second gate structure extends in the second direction crossing the first direction and is arranged in parallel with the first gate structure in the first direction in plan view, and
the void is formed in an area defined by the first and second fin structures and the first and second gate structures in plan view.

8. The semiconductor device of claim 1 , wherein a height of the first fin structure under the first gate electrode is greater than a height of the first fin structure under the source/drain structure.

9. The semiconductor device of claim 1
wherein the first and second fin structures protrude from the first and second fin sidewall spacers, respectively.

10. The semiconductor device of claim 9 , further comprising first gate sidewall spacers disposed on opposing side faces of the first gate structure,
wherein a material of the first gate sidewall spacers is the same as a material of the first and second fin sidewall spacers.

11. A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a first fin structure and a second fin structure, upper portions of the first and second fin structures being exposed from the isolation insulating layer;
a first gate structure and a second gate structure disposed over parts of the first and second fin structures;
first and second fin sidewall spacers covering lower portions of the first and second fin structures exposed from the isolation insulating layer, respectively;
first to third source/drain structures formed on the upper portions of the first and second fin structures above the first and second fin sidewall spacers, and wrapping side surfaces and a top surface of each of the exposed first and second fin structures;
an interlayer dielectric layer disposed over the first and second gate structures and the first to third source/drain structures;
a silicide layer disposed on the first to third source/drain structures; and
a contact plug formed in the interlayer dielectric layer and connected to the silicide layer disposed on the second source/drain structure, wherein:
the first to third source/drain structures are arranged in this order and the second source/drain structure is disposed between the first and second gate structures,
a void is formed between the second source/drain structure and the isolation insulating layer, and
the silicide layer is formed on an entire outer surface of the first to third source/drain structures except in the void.

12. The semiconductor device of claim 11 , wherein a height of the first fin structure under the first gate electrode is greater than a height of the first fin structure under the first source/drain structure.

13. The semiconductor device of claim 11 , further comprising first and second gate sidewall spacers disposed on opposing side faces of the first and second gate structures, respectively,
wherein a material of the first and second gate sidewall spacers is the same as a material of the first and second fin sidewall spacers.

14. The semiconductor device of claim 13 , wherein the material is a low-k dielectric material.

15. The semiconductor device of claim 11 , wherein:
parts of the first and second fin sidewall spacers are disposed in the void, and
entire side surfaces of the parts are exposed in the void.

16. The semiconductor device of claim 11 , further comprising an etch-stop-layer disposed between the silicide layer and the interlayer dielectric layer,
wherein the etch stop layer is separated from the first to third source/drain structures by the silicide layer.

17. A semiconductor device comprising a FinFET, the FinFET comprising:
a first fin structure and a second fin structure, an upper portion of each of which protrudes from an isolation insulating layer disposed over a substrate;
a gate structure disposed over the first and second fin structures;
a first source/drain epitaxial layer formed on the upper portion of the first fin structure and a second source/drain epitaxial layer formed on the upper portion of the second fin structure; and
a void disposed between the first source/drain epitaxial layer and the isolation insulating layer,
wherein a height of the first and second fin structures under the gate structure is greater than heights of the first and second fin structures under the source/drain structure, and
the second source/drain epitaxial layer covers an part of a lateral end surface and parts of side surfaces of the first fin structure under the second source/drain structure.

18. The semiconductor device of claim 17 , further comprising:
fin sidewall spacers covering lower portions of the upper portion of the first and second fin structures protruding from the isolation insulating layer, respectively

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fung Ka-Hing

Classifications

• H01L21/823814

  Electricity · mapped topic

• H01L29/267

  Electricity · mapped topic

• H01L29/515

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic