Device for a FinFET

Patent metadata

Field	Value
Publication number	US-10157919-B2
Application number	US-201715676354-A
Country	US
Kind code	B2
Filing date	Aug 14, 2017
Priority date	Jan 12, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A semiconductor device includes a semiconductor substrate, multiple fins formed on a front surface of the semiconductor substrate, a stress layer formed on a top surface of the fins, multiple strip-shaped gate structures formed above the stress layers, each of which extending in a direction substantially perpendicular to a direction of the fins, a contact hole etch stop layer covering the front surface of the semiconductor substrate, sidewalls of the fins, and top surfaces and sidewalls of the stress layers, a first interlayer dielectric layer over the contact hole etch stop layer, the first interlayer dielectric layer including filling voids formed therein, and a top surface of the first interlayer dielectric layer being below the top surfaces of the stress layers, a barrier liner layer over the first interlayer dielectric layer, and a second interlayer dielectric layer over the barrier liner layer and the contact hole etch stop layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a plurality of fins formed on a front surface of the semiconductor substrate;
a stress layer formed on a top surface of each of the fins;
a plurality of strip-shaped gate structures formed above the stress layers, each of the strip-shaped gate structures extending in a direction substantially perpendicular to a direction of the fins;
a contact hole etch stop layer covering the front surface of the semiconductor substrate, sidewalls of the fins, and top surfaces and sidewalls of the stress layers;
a first interlayer dielectric layer over the contact hole etch stop layer, the first interlayer dielectric layer including filling voids formed therein, and a top surface of the first interlayer dielectric layer being below the top surfaces of the stress layers and above the filling voids;
a barrier liner layer over the first interlayer dielectric layer; and
a second interlayer dielectric layer over the barrier liner layer and the contact hole etch stop layer, wherein the second interlayer dielectric layer has a top surface higher than a top surface of the stress layer on each of the fins.

2. The semiconductor device of claim 1 , wherein the stress layers comprise SiGe or SiC.

3. The semiconductor device of claim 1 , wherein the barrier liner layer comprises silicon oxide or silicon nitride.

4. The semiconductor device of claim 1 , further comprising a high aspect ratio pad (HARP) layer between the first interlayer dielectric layer and the contact hole etch stop layer.

5. An electronic apparatus comprising the semiconductor device of claim 1 .

6. The semiconductor device of claim 1 , wherein the barrier liner layer has a density higher than a density of the first interlayer dielectric layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zeng Yizhi

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10W20/097

  by thermally treating · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title