N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch

Patent metadata

Field	Value
Publication number	US-9257429-B2
Application number	US-201514665988-A
Country	US
Kind code	B2
Filing date	Mar 23, 2015
Priority date	Jun 13, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a first set of semiconductor fins aligned in a first direction on the substrate, one or more of the semiconductor fins in the first set including at least one channel region and at least two source/drain regions of finFETs;
a second set of semiconductor fins aligned in the first direction on the substrate one or more of the semiconductor fins in the second set including at least one channel region and at least two source/drain regions of finFETs;
a third set of semiconductor fins aligned in the first direction on the substrate, one or more of the semiconductor fins in the third set including at least one channel region and at least two source/drain regions of finFETs;
a first power conductor over semiconductor fins in the first set and the third set between the first set and the third set;
a patterned gate conductor layer including a plurality of gate elements on corresponding fins in the first and second sets of semiconductor fins, the gate elements being disposed over channel regions of the corresponding semiconductor fins;
at least one patterned conductor layer overlying the patterned gate conductor layer; and
a plurality of interlayer connectors, including interlayer connectors aligned over corresponding semiconductor fins in the first and second sets and connected to the gate elements of particular finFETs on the corresponding fins.

2. The integrated circuit of claim 1 , wherein semiconductor fins in the first set extend to respective semiconductor fins in the third set.

3. The integrated circuit of claim 1 , comprising:
a fourth set of semiconductor fins aligned in the first direction on the substrate, one or more of the semiconductor fins in the third set including at least one channel region and at least two source/drain regions of finFETs; and
a second power conductor over semiconductor fins in the second set and the fourth set between the second set and the fourth set.

4. The integrated circuit of claim 3 , wherein semiconductor fins in the second set extend to respective semiconductor fins in the fourth set.

5. The integrated circuit of claim 1 , comprising:
an inter-block isolation structure on the substrate having a first side and a second side, and wherein semiconductor fins in the first set have first ends proximal to the first side of the inter-block isolation structure and semiconductor fins in the second set have second ends proximal to the second side of the inter-block isolation structure.

6. The integrated circuit of claim 5 , including stressor structures on the first and second ends of the semiconductor fins in the first and second sets.

7. The integrated circuit of claim 1 , wherein the interlayer connectors have first axis and second axis contact pitches, where the first axis is aligned in the first direction and the second axis is perpendicular to the first axis; and
said at least one channel region and said at least two source/drain regions have in combination three times the first axis contact pitch.

8. The integrated circuit of claim 1 , including interlayer connectors aligned over and connected to one or both of the source/drain regions of the particular finFETs.

9. The integrated circuit of claim 1 , including an additional patterned conductor layer beneath said at least one patterned conductor layer.

10. The integrated circuit of claim 1 , wherein the channel regions in the first set are n-channel and the channel regions in the second set are p-channel.

11. The integrated circuit of claim 3 , wherein the channel regions in the third set are n-channel and the channel regions in the fourth set are p-channel.

12. The integrated circuit of claim 1 , comprising:
interlayer connectors aligned over corresponding semiconductor fins in the first and second sets, which connect to a conductor in the patterned conductor layer that connects to a source/drain region on one finFET on a semiconductor fin in the first set of semiconductor fins and to a source/drain region on another finFET on a semiconductor fin in the second sets of semiconductor fins.

13. The integrated circuit of claim 1 , wherein the source/drain regions on the semiconductor fins for finFETs on the first set of semiconductor fins have uniform structures, and the source/drain regions on the semiconductor fins for finFETs on the second set of semiconductor fins have uniform structures.

14. The integrated circuit of claim 1 , comprising:
a plurality of patterned conductor layers, including said at least one patterned conductor layer, one or more conductors in the plurality of patterned conductor layers and the interlayer connectors being arranged to connect a semiconductor fin in the first set to a semiconductor fin in the second set, arranged to connect a first gate element on a semiconductor fin in the first set with a second gate element on a semiconductor fin in the second set, and arranged to connect a power conductor to at least one semiconductor fin in one of the first and second sets.

15. The integrated circuit of claim 1 , wherein semiconductor fins in the second set are aligned end-to-end with semiconductor fins in the first set.

16. The integrated circuit of claim 1 , wherein semiconductor fins in the third set are aligned end-to-end with semiconductor fins in the first set.

17. The integrated circuit of claim 3 , wherein semiconductor fins in the fourth set are aligned end-to-end with semiconductor fins in the second set.

18. The integrated circuit of claim 1 , wherein semiconductor fins in the second set are offset relative to semiconductor fins in the first set.

19. A tangible non-transitory computer readable medium storing computer readable instructions executable by a computer system, including:
instructions executable by the computer system to transform a hardware description language circuit representation into a physical circuit representation, the physical circuit representation comprising:
a substrate;
a first set of semiconductor fins aligned in a first direction on the substrate, one or more of the semiconductor fins in the first set including at least one channel region and at least two source/drain regions of finFETs;
a second set of semiconductor fins aligned in the first direction on the substrate one or more of the semiconductor fins in the second set including at least one channel region and at least two source/drain regions of finFETs;
a third set of semiconductor fins aligned in the first direction on the substrate, one or more of the semiconductor fins in the third set including at least one channel region and at least two source/drain regions of finFETs;
a first power conductor over semiconductor fins in the first set and the third set between the first set and the third set;
a patterned gate conductor layer including a plurality of gate elements on corresponding fins in the first and second sets of semiconductor fins, the gate elements being disposed over channel regions of the corresponding semiconductor fins;
at least one patterned conductor layer overlying the patterned gate conductor layer; and
a plurality of interlayer connectors, including interlayer connectors aligned over corresponding semiconductor fins in the first and second sets and connected to the gate elements of particular finFETs on the corresponding fins.

20. The tangible non-transitory computer readable medium of claim 19 , wherein semiconductor fins in the first set extend to respective semiconductor fins in the third set.

Assignees

• Synopsys Inc

Inventors

• Moroz Victor
• Sherlekar Deepak D

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H10D84/853 Primary

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D89/10

  Integrated device layouts · CPC title