Bulk to silicon on insulator device

Patent metadata

Field	Value
Publication number	US-9991339-B2
Application number	US-201615364578-A
Country	US
Kind code	B2
Filing date	Nov 30, 2016
Priority date	Apr 6, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor fin formed on a substrate;
a gate stack formed over a channel region of a first surface of the semiconductor fin;
an etch stop layer directly adjacent to and in direct contact with a sidewall of the semiconductor fin; and
a semiconductor material directly formed on exposed portions of a second surface of the semiconductor fin, the second surface opposite to and not coplanar with the first surface of the semiconductor fin.

2. The device of claim 1 , further comprising a second insulator layer formed over the semiconductor material and the insulator layer of the substrate.

3. The device of claim 1 , wherein the channel region comprises an amorphous semiconductor material.

4. The device of claim 3 , further comprising a conductive contact material formed on the semiconductor material.

5. The device of claim 1 , wherein the substrate is a semiconductor on insulator substrate comprising an insulator layer and the semiconductor fin is formed on the insulator layer.

6. The device of claim 1 , wherein the semiconductor material comprises epitaxially grown crystalline semiconductor material.

7. The device of claim 1 , wherein the bonding film comprises a dielectric material.

8. A semiconductor device comprising:
a semiconductor fin formed on a substrate;
a gate stack formed over a channel region of a first surface of the semiconductor fin;
an etch stop layer directly adjacent to and in direct contact with a sidewall of the semiconductor fin;
a bonding film formed on the gate stack and the first surface of the semiconductor fin;
a handle wafer coupled to the bonding film; and
a semiconductor material directly formed on exposed portions of a second surface of the semiconductor fin, the second surface opposite to and not coplanar with the first surface of the semiconductor fin.

9. The device of claim 8 , further comprising a dielectric layer formed over the semiconductor material.

10. The device of claim 9 , further comprising a conductive contact formed on a surface of the semiconductor material.

11. The device of claim 8 , further comprising an interlayer dielectric formed adjacent to the gate stack between the semiconductor fin and the bonding film.

12. The device of claim 11 , further comprising an etch stop layer formed between the interlayer dielectric and the semiconductor material.

13. The device of claim 12 , wherein the etch stop layer comprises a nitride.

14. The device of claim 8 , wherein the channel region comprises an amorphous semiconductor material.

Assignees

• IBM

Inventors

• Hook Terence B
• Rubin Joshua M
• Yamashita Tenko

Classifications

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P14/272

  using mask materials other than SiO2 or SiN · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title