Wiring structures and semiconductor devices

Patent metadata

Field	Value
Publication number	US-10229876-B2
Application number	US-201615073640-A
Country	US
Kind code	B2
Filing date	Mar 17, 2016
Priority date	May 19, 2015
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

First claim

What is claimed is:

1. A wiring structure, comprising:
a substrate;
a lower insulation layer on the substrate;
a lower wiring in the lower insulation layer;
a multi-layered etch-stop layer covering the lower wiring and the lower insulation layer, wherein a thickness of the multi-layered etch-stop layer over the lower wiring is greater than a thickness of the multi-layered etch-stop layer over the lower insulation layer, the multi-layered etch-stop layer including:
a first etch-stop layer covering the lower wiring and including a metallic dielectric material, wherein the first etch-stop layer includes a first portion formed on the lower wiring and a second portion formed on the lower insulation layer, and wherein the first portion is thicker than the second portion; and
a second etch-stop layer on the first etch-stop layer and the lower insulation layer;

an insulating interlayer on the second etch-stop layer; and
a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer to be electrically connected to the lower wiring.

2. The wiring structure of claim 1 , wherein the first etch-stop layer includes a dielectric metal nitride.

3. The wiring structure of claim 1 , wherein the second etch-stop layer includes a non-metallic dielectric material.

4. The wiring structure of claim 3 , wherein the second etch-stop layer includes at least one selected from the group consisting of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride and silicon oxycarbide.

5. The wiring structure of claim 1 , wherein the first etch-stop layer continuously extends on the lower wiring and the lower insulation layer.

6. The wiring structure of claim 1 , wherein the second etch-stop layer has a uniform thickness along the first portion and the second portion of the first etch-stop layer.

7. The wiring structure of claim 1 , wherein the conductive pattern extends commonly through the first portion and the second portion of the first etch-stop layer, and
the conductive pattern contacts top surfaces of the lower wiring and the lower insulation layer.

8. The wiring structure of claim 7 , wherein the conductive pattern partially overlaps the top surface of the lower wiring and is staggered with the lower wiring.

9. The wiring structure of claim 1 , wherein the first etch-stop layer is selectively formed on a top surface of the lower wiring with respect to the top surface of the lower insulation layer.

10. The wiring structure of claim 9 , wherein the conductive pattern is landed on the top surface of the lower wiring, and
a bottom of conductive pattern contacts the top surface of the lower wiring.

11. The wiring structure of claim 1 , wherein a top portion of the second etch-stop layer contacts the conductive pattern and is higher than a top surface of the second etch-stop layer over the lower insulation layer.

12. A wiring structure, comprising:
a substrate;
a lower insulation layer on the substrate;
a lower wiring in the lower insulation layer;
a first etch-stop layer covering the lower wiring and the lower insulation layer, the first etch-stop layer being relatively thicker on the lower wiring than on the lower insulation layer;
a second etch-stop layer on the first etch-stop layer, the second etch-stop layer including a material different from that of the first etch-stop layer;
an insulating interlayer on the second etch-stop layer; and
a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

13. The wiring structure of claim 12 , wherein the first etch-stop layer includes a metallic dielectric material, and the second etch-stop layer includes a non-metallic dielectric material.

14. The wiring structure of claim 13 , wherein the first etch-stop layer includes aluminum nitride, and the second etch-stop layer includes silicon carbide or silicon oxycarbide.

15. The wiring structure of claim 12 , wherein the conductive pattern contacts top surfaces of the lower wiring and the lower insulation layer.

16. The wiring structure of claim 12 , wherein a top portion of the second etch-stop layer contacts the conductive pattern and is higher than a top surface of the second etch-stop layer over the lower insulation layer.

17. A wiring structure, comprising:
a substrate;
a lower insulation layer on the substrate;
a lower wiring in the lower insulation layer;
a multi-layered etch-stop layer covering the lower insulation layer and the lower wiring and having a first etch-stop layer covering a peripheral portion of the lower wiring and the lower insulation layer and a second etch-stop layer on the first etch-stop layer, wherein a top surface of the first etch-stop layer on the lower wiring is higher than a top surface of the first etch-stop layer on the lower insulation layer and a top surface of the second etch-stop layer over the lower wiring is higher than a top surface of the second etch-stop layer over the lower insulation layer;
an insulating interlayer on the second etch-stop layer; and
a conductive pattern extending through the insulating interlayer and the multi-layered etch-stop layer such that the conductive pattern is enclosed by the insulating interlayer and the multi-layered etch-stop layer and electrically connected to the lower wiring.

18. The wiring structure of claim 17 , wherein a top surface of the conductive pattern is coplanar with a top surface of the insulating interlayer.

19. The wiring structure of claim 17 , wherein the wiring structure includes a pair of lower wirings that are adjacent to one another and wherein the first etch-stop layer has a same thickness on the pair of lower wirings and a thickness of the first etch-stop layer on the lower wiring is greater than a thickness of the first etch-stop layer on the lower insulation layer.

20. The wiring structure of claim 17 , wherein a top portion of the second etch-stop layer contacts the conductive pattern and is higher than a top surface of the second etch-stop layer over the lower insulation layer.

Assignees

• Kim Jun Jung
• Kim Young Bae
• Kim Jong Sam
• Park Jin Hyeung
• Ahn Jeong Hoon
• Oh Hyeok Sang
• Lee Kyoung Woo
• Lee Hyo Seon
• Jang Suk Hee
• Samsung Electronics Co Ltd

Inventors

• Kim Jun-Jung
• Kim Young-Bae
• Kim Jong-Sam
• Park Jin-Hyeung
• Ahn Jeong-Hoon
• Oh Hyeok-Sang
• Lee Kyoung-Woo
• Lee Hyo-Seon
• JANG Suk-Hee

Classifications

• H10W20/059

  by reflowing or applying pressure · CPC title

• H10W20/043

  for electroplating · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title