Self-aligned dual-height isolation for bulk FinFET

Patent metadata

Field	Value
Publication number	US-9564486-B2
Application number	US-201514839378-A
Country	US
Kind code	B2
Filing date	Aug 28, 2015
Priority date	Nov 19, 2013
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first isolation region located between fins of a first group of fins and between fins of a second group of fins, the first group of fins and the second group of fins being formed in a bulk semiconductor substrate; and
a second isolation region between the first group of fins and the second group of fins, the second isolation region extending through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region, wherein the second isolation region and the first group of fins and the second group of fins are separated by a portion of the first isolation region that has a length equivalent to half the distance between two adjacent fins.

2. The semiconductor structure of claim 1 , wherein the first isolation region separates each individual fin of the first group of fins and the second group of fins from one another and the second isolation region separates the first group of fins from the second group of fins.

3. The semiconductor structure of claim 1 , wherein the first and second isolation regions comprise a dielectric material.

4. The semiconductor structure of claim 1 , wherein the dielectric material is silicon dioxide.

5. The semiconductor structure of claim 1 , wherein a topmost surface of the second isolation region is greater than a topmost surface of each of the first group of fins and the second group of fins.

6. The semiconductor structure of claim 1 , wherein a topmost surface of the first isolation region is less than a topmost surface of each of the first and second fins.

7. The semiconductor structure of claim 1 , wherein a bottommost surface of the first isolation region is coplanar with a bottommost surface of each of the first group of fins and the second group of fins.

8. The semiconductor structure of claim 1 , wherein at least one sidewall surface of the first isolation region directly contacts a sidewall surface of one of the fins of the first group of fins or one of the fins of the second group of fins.

9. The semiconductor structure of claim 1 , wherein the second isolation region has a bottommost surface that contacts a sub-surface of the bulk semiconductor substrate.

10. The semiconductor structure of claim 1 , wherein the first isolation region comprises a first dielectric material and the second isolation region comprises a second dielectric material.

11. The semiconductor structure of claim 1 , wherein an upper sidewall portion and a topmost surface of each fin of the first group of fins and the second group of fins are exposed.

12. The semiconductor structure of claim 11 , wherein an nFET device is formed on exposed surfaces of each fin of the first group of fins and a pFET device is formed on exposed surfaces of each fin of the second group of fins.

13. The semiconductor structure of claim 11 , wherein a pFET device is formed on exposed surfaces of each fin of the first group of fins and an nFET device is formed on exposed surfaces of each fin of the second group of fins.

Assignees

• IBM
• Globalfoundries Inc
• Renesas Electronics Corp

Inventors

• Akarvardar Murat Kerem
• Bentley Steven John
• Cheng Kangguo
• Doris Bruce B
• Fronheiser Jody
• Jacob Ajey Poovannummoottil
• Khakifirooz Ali
• Nagumo Toshiharu

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L21/76229

  Electricity · mapped topic