Self-aligned gate edge and local interconnect and method to fabricate same

Patent metadata

Field	Value
Publication number	US-9831306-B2
Application number	US-201315024750-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Dec 19, 2013
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor fin disposed above a substrate and having a length in a first direction;
a gate structure disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction, wherein the gate structure has an uppermost surface; and
a pair of gate edge isolation structures centered with the semiconductor fin, wherein a first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure, and wherein the pair of gate edge isolation structures has an uppermost surface co-planar with or above the uppermost surface of the gate structure.

2. The semiconductor structure of claim 1 , further comprising:
source and drain regions disposed in the semiconductor fin, on either side of the gate structure; and
a first trench contact disposed over the source region and a second trench contact disposed over the drain region, each of the first and second trench contacts having a first end opposite a second end in the second direction, wherein the first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the first trench contact and to the first end of the second trench contact, and the second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the first trench contact and to the second end of the second trench contact.

3. The semiconductor structure of claim 1 , further comprising:
a second semiconductor fin disposed above the substrate and having a length in the first direction, the second semiconductor fin spaced apart from the first semiconductor fin;
a second gate structure disposed over the second semiconductor fin, the second gate structure having a first end opposite a second end in the second direction, wherein the second of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the second gate structure; and
a third gate edge isolation structure disposed directly adjacent to the second end of the second gate structure, wherein the third gate edge isolation structure and the second of the pair of gate edge isolation structures are centered with the second semiconductor fin.

4. The semiconductor structure of claim 3 , further comprising:
a local interconnect disposed above and electrically coupling the first and second gate structures.

5. The semiconductor structure of claim 4 , wherein the local interconnect is self-aligned with the pair of and the third gate edge isolation structures.

6. The semiconductor structure of claim 3 , wherein the gate structure is an N-type gate structure, and the second gate structure is a P-type gate structure.

7. The semiconductor structure of claim 1 , wherein the gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

8. The semiconductor structure of claim 1 , wherein the pair of gate edge isolation structures comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and a combination thereof.

9. A semiconductor structure, comprising:
a semiconductor fin disposed above a substrate and having a length;
alternating source/drain and channel regions disposed in the length of the semiconductor fin, each source/drain region having an associated trench contact disposed over the semiconductor fin, and each channel region having an associated gate structure disposed over the semiconductor fin; and
a plurality of gate edge isolation structures, wherein an adjacent trench contact and gate structure are separated by one gate edge isolation structure of the plurality of gate edge isolation structures; and
a gate local interconnect disposed above one of the gate structures and between a pair of the plurality of gate edge isolation structures.

10. The semiconductor structure of claim 9 , further comprising:
a dielectric cap disposed on the gate local interconnect, the dielectric cap disposed between the pair of the plurality of gate edge isolation structures.

11. The semiconductor structure of claim 9 , further comprising:
a trench contact local interconnect disposed above one of the trench contacts and between a second pair of the plurality of gate edge isolation structures.

12. The semiconductor structure of claim 11 , further comprising:
a dielectric cap disposed on the trench contact local interconnect, the dielectric cap disposed between the second pair of the plurality of gate edge isolation structures.

13. The semiconductor structure of claim 9 , wherein each gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

14. The semiconductor structure of claim 9 , wherein each of the plurality of gate edge isolation structures comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and a combination thereof.

15. A semiconductor structure, comprising:
a semiconductor fin disposed above a substrate and having a length;
alternating source/drain and channel regions disposed in the length of the semiconductor fin, each source/drain region having an associated trench contact disposed over the semiconductor fin, and each channel region having an associated gate structure disposed over the semiconductor fin; and
a plurality of gate edge isolation structures, wherein an adjacent trench contact and gate structure are separated by one gate edge isolation structure of the plurality of gate edge isolation structures; and
a trench contact local interconnect disposed above one of the trench contacts and between a pair of the plurality of gate edge isolation structures.

16. The semiconductor structure of claim 15 , further comprising:
a dielectric cap disposed on the trench contact local interconnect, the dielectric cap disposed between the pair of the plurality of gate edge isolation structures.

17. The semiconductor structure of claim 15 , wherein each gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

18. The semiconductor structure of claim 15 , wherein each of the plurality of gate edge isolation structures comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and a combination thereof.

19. A method of fabricating a semiconductor structure, the method comprising:
forming first and second parallel semiconductor fins above a substrate;
forming dummy spacers adjacent the sidewalls of each of the first and second semiconductor fins, wherein the dummy spacers of the first semiconductor fin are non-continuous with the dummy spacers of the second semiconductor fin;
forming an isolation structure between the dummy spacers of the first and second semiconductor fins;
removing the dummy spacers; and
forming a first replacement gate structure over the first semiconductor fin and a second replacement gate structure over the second semiconductor fin, wherein the first and second gate structures are directly adjacent to, and separated from one another by, the isolation structure.

20. The method of claim 19 , further comprising:
forming a first pair of trench contacts over the first semiconductor fin and a second pair of trench contacts over the second semiconductor fin, wherein the first and pairs of trench con

Assignees

• Intel Corp

Inventors

• Webb Milton Clair
• Bohr Mark
• Ghani Tahir
• Liao Szuya S

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic