Apparatus for FinFETs

Patent metadata

Field	Value
Publication number	US-10068905-B2
Application number	US-201615178045-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Apr 13, 2012
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A device comprises a first inverter comprising a first p-type transistor (PU) and a first n-type transistor (PD), a second inverter cross-coupled to the first inverter comprising a second PU and a second PD, a first pass-gate transistor coupled between the first inverter and a first bit line and a second pass-gate transistor coupled between the second inverter and a second bit line, wherein at least one transistor has a two-stage fin structure, and wherein a width of a bottom portion of the two-stage fin structure is greater than a width of an upper portion of the two-stage fin structure.

First claim

What is claimed is:

1. A device comprising:
a first inverter comprising a first p-type pull-up transistor (PU) and a first n-type pull-down transistor (PD);
a second inverter cross-coupled to the first inverter comprising a second PU and a second PD;
a first pass-gate transistor coupled between the first inverter and a first bit line; and
a second pass-gate transistor coupled between the second inverter and a second bit line, wherein the second pass-gate transistor has a two-stage fin structure comprising multiple fin lines, and wherein a width of a bottom portion of the two-stage fin structure is greater than a width of an upper portion of the two-stage fin structure, and wherein the second pass-gate transistor comprises a merged drain/source region covering the multiple fin lines, and wherein the second PU comprises a drain/source region covering a single fin line immediately adjacent to the multiple fin lines, and wherein a doping concentration of an upper region of the bottom portion of the two-stage fin structure is higher than a doping concentration of an upper region of the upper portion of the two-stage fin structure.

2. The device of claim 1 , wherein:
the first PU is connected in series with the first PD; and
the second PU is connected in series with the second PD.

3. The device of claim 1 , wherein:
the number of fin lines in the upper portion of the two-stage fin structure is greater than the number of fin lines in the bottom portion of the two-stage fin structure.

4. The device of claim 1 , wherein:
the bottom portion and the upper portion of the two-stage fin structure are trapezoidal in shape.

5. The device of claim 1 , wherein:
the upper portion of the two-stage fin structure comprises two fin lines over the bottom portion of the two-stage fin structure.

6. The device of claim 1 , wherein:
the first PU comprises a first two-stage fin structure, and wherein an upper portion of the first two-stage fin structure comprises a single fin line; and
the first PD and the second PD comprise a second two-stage fin structure, and wherein an upper portion of the second two-stage fin structure comprises multiple fin lines.

7. The device of claim 1 , wherein:
the first pass-gate transistor comprises a first fin structure, and wherein an upper portion of the first fin structure comprises a first fin line and a second fin line over a bottom portion of the first fin structure; and
the second pass-gate transistor comprises a third fin line, a fourth fin line and a fifth fin line over the bottom portion of the two-stage fin structure.

8. The device of claim 7 , wherein:
a width of the first fin line of the upper portion of the first fin structure is approximately equal to a width of the second fin line of the upper portion of the first fin structure; and
a width of the first fin line of the upper portion of the first fin structure is approximately equal to a width of the third fin line of the two-stage fin structure.

9. The device of claim 1 , wherein:
one transistor of the first PU, the first PD, the second PU, the second PD comprises a third fin structure rectangular in shape; and
another transistor of the first PU, the first PD, the second PU, the second PD comprises a fourth fin structure, and wherein the fourth fin structure is a two-stage fin structure.

10. The device of claim 1 , wherein:
the device is a six-transistor memory cell comprising four two-stage fin structures and four gate regions.

11. The device of claim 10 , wherein:
the four two-stage fin structures are placed in parallel; and
at least one two-stage fin structure is orthogonal to one of the four gate regions.

12. A device comprising:
an isolation region formed in a substrate; and
a six-transistor memory cell over the substrate, wherein the six-transistor memory cell comprises four n-type transistors and two p-type transistors, and wherein:
a first n-type transistor comprises a first two-stage fin structure comprising a bottom portion enclosed by the isolation region and an upper portion protruding above the isolation region, wherein a width of the bottom portion of the first two-stage fin structure is greater than a width of the upper portion of the first two-stage fin structure, wherein the upper portion of the first two-stage fin structure comprises multiple fin lines and a merge drain/source region of the first n-type transistor covers the multiple fin lines, and wherein a p-type doping concentration of an upper region of the bottom portion of the first two-stage fin structure is higher than a p-type doping concentration of an upper region of the upper portion of the first two-stage fin structure; and
a first p-type transistor comprises a second two-stage fin structure comprising a bottom portion enclosed by the isolation region and an upper portion protruding above the isolation region, wherein a width of the bottom portion of the second two-stage fin structure is greater than a width of the upper portion of the second two-stage fin structure, wherein the upper portion of the second two-stage fin structure comprises a single fin line and a drain/source region of the first p-type transistor covers the single fin line, and wherein a width of the merged drain/source region of the first n-type transistor is greater than a width of the drain/source region of the first p-type transistor.

13. The device of claim 12 , wherein:
the upper portion of the first two-stage fin structure comprises two fin lines.

14. The device of claim 12 , wherein:
the upper portion of the first two-stage fin structure is rectangular in shape; and
the bottom portion of the first two-stage fin structure is rectangular in shape.

15. The device of claim 12 , wherein:
the upper portion of the first two-stage fin structure is trapezoidal in shape; and
the bottom portion of the first two-stage fin structure is trapezoidal in shape.

16. A memory cell comprising:
a first inverter comprising:
a first p-type pull-up transistor (PU) having a two-stage fin structure, wherein a width of a bottom portion of the two-stage fin structure is greater than a width of an upper portion of the two-stage fin structure, and wherein an n-type doping concentration of an upper region of the bottom portion of the two-stage fin structure is higher than an n-type doping concentration of an upper region of the upper portion of the two-stage fin structure; and
a first n-type pull-down transistor (PD) having the two-stage fin structure, wherein the first PU is connected in series with the first PD;

a second inverter cross-coupled to the first inverter comprising:
a second PU having the two-stage fin structure; and
a second PD having the two-stage fin structure, wherein the second PU is connected in series with the second PD;

a first pass-gate transistor having the two-stage fin structure comprising first multiple fin lines, wherein the first pass-gate transistor is coupled between the first inverter and a first bit line, and wherein the first pass-gate transistor comprises a first merged drain/source region covering the first multiple fin lines; and
a second pass-gate transistor having the two-stage fin structure comprising second multiple fin lines, wherein the second pass-gate transistor is coupled between the second inverter and a second bit line, and wherein the second pass-gate transistor comprises a second merged drain/source region covering the second multiple fin lines.

17. The memory cell of claim 16 , wherein:
the first PD is formed by two FinFETs connected in parallel;
the second PD is formed b

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon-Jhy

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76232

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L29/7853

  Electricity · mapped topic