Vertical field effect transistor with bottom spacer

Patent metadata

Field	Value
Publication number	US-11646373-B2
Application number	US-202117516994-A
Country	US
Kind code	B2
Filing date	Nov 2, 2021
Priority date	Jan 9, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.

First claim

The invention claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming at least one semiconductor vertical fin on a semiconductor substrate, the semiconductor substrate defining a longitudinal axis;
forming first and second isolation regions adjacent respective opposed longitudinal ends of the semiconductor vertical fin;
forming a recessed segment in the first isolation region adjacent one longitudinal end of the semiconductor vertical fin;
forming a bottom source/drain region within the semiconductor substrate beneath the semiconductor vertical fin;
forming a first top source/drain region on the semiconductor vertical fin;
forming a bottom spacer on the first and second isolation regions and upper surface portions of the bottom source/drain region, wherein a first spacer segment of the bottom spacer is at least partially accommodated within the recessed segment of the first isolation region and extends onto the bottom source/drain region; and
forming a functional metal gate structure along the semiconductor vertical fin.

2. The method of claim 1 including forming trench openings in the semiconductor substrate adjacent the opposed longitudinal ends of the semiconductor vertical fin.

3. The method of claim 2 including forming a dielectric liner on the semiconductor substrate, the dielectric liner lining the trench openings in the semiconductor substrate and covering surface portions of the bottom source/drain region.

4. The method of claim 3 wherein forming the first and second isolation regions includes depositing a dielectric fill relative to the semiconductor substrate, the dielectric fill formed within the trench openings and extending above the bottom source/drain region.

5. The method of claim 4 including forming a sacrificial liner relative to the semiconductor substrate to cover the dielectric fill and the semiconductor vertical fin.

6. The method of claim 5 including depositing a sacrificial material onto at least portions of the sacrificial liner above the first and second isolation regions.

7. The method of claim 6 wherein the sacrificial material comprises an organic planarization layer.

8. The method of claim 6 including removing portions of the sacrificial liner to expose the dielectric fill above the bottom source/drain region.

9. The method of claim 8 including removing exposed portions of the dielectric fill above the bottom source/drain region whereby the recessed segment in the first isolation region is formed.

10. The method of claim 9 including removing the dielectric liner from the semiconductor vertical fin and exposed portions on the bottom source/drain region wherein a liner segment of the dielectric liner extends onto the bottom source/drain region.

11. The method of claim 10 wherein forming the bottom spacer includes extending a second spacer segment from the liner segment to the semiconductor vertical fin.

12. A method for fabricating a semiconductor device, comprising:
forming a semiconductor vertical fin on a substrate;
forming first and second trenches within the substrate adjacent respective opposed longitudinal ends of the semiconductor vertical fin;
forming a bottom source/drain region beneath the vertical semiconductor fin;
forming a dielectric liner within the first and second trenches and onto at least surface portions of the bottom source/drain region;
depositing a dielectric fill within each of the first and second trenches and onto the dielectric liner, the dielectric fill extending vertically above the bottom source/drain region;
forming a bottom spacer onto the dielectric fill;
at least partially covering a first longitudinal end of the bottom source/drain region with a first spacer segment of the bottom spacer;
at least partially covering a second longitudinal end of the bottom source/drain region with a liner segment of the dielectric liner;
forming a first top source/drain region on the semiconductor vertical fin; and
forming at least one functional metal gate structure along the semiconductor vertical fin.

13. The method of claim 12 including forming an undercut in the dielectric fill within the first trench and wherein at least partially covering the first longitudinal end of the bottom source/drain region includes disposing the first spacer segment of the bottom spacer in the undercut.

14. The method of claim 13 wherein forming the bottom spacer includes extending a second spacer segment of the bottom spacer adjacent the first trench, the second spacer segment extending below an upper surface portion of the bottom source/drain region.

15. The method of claim 14 wherein the first spacer segment and the second spacer segment of the bottom spacer are monolithically formed.

16. The method of claim 14 wherein forming the bottom spacer includes configuring the first spacer segment to taper to define a decreased height adjacent the semiconductor vertical fin.

17. The method of claim 13 wherein forming the bottom spacer includes forming a third spacer segment of the bottom spacer disposed on an upper surface portion of the bottom source/drain region adjacent the second longitudinal end of the bottom source/drain region.

18. The method of claim 14 wherein forming the bottom spacer includes extending the first spacer segment and the second spacer segment to contact the semiconductor vertical fin.

19. The method of claim 17 wherein forming the bottom spacer includes configuring the third spacer segment to taper to define a decreased height adjacent the semiconductor vertical fin.

20. A method for fabricating a semiconductor device, comprising:
forming a semiconductor vertical fin on a semiconductor substrate, the semiconductor substrate defining a longitudinal axis;
forming first and second isolation regions adjacent respective opposed first and second longitudinal ends of the semiconductor vertical fin;
forming a recessed segment in the first isolation region adjacent one longitudinal end of the semiconductor vertical fin;
forming top and bottom source/drain regions relative to the semiconductor vertical fin;
forming a bottom spacer onto at least upper surface portions of the bottom source/drain region, wherein a spacer segment of the bottom spacer disposed adjacent the first longitudinal end of the bottom source/drain region includes a horizontal component and a vertical component, the vertical component extending downwardly from the horizontal component, the horizontal component and the vertical component of the spacer segment configured to cover the first longitudinal end of the bottom source/drain region.

Assignees

• IBM

Inventors

• Waskiewicz Christopher J
• Xie Ruilong
• Strane Jay William
• Jagannathan Hemanth

Classifications

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title