Stacked fet with flexible inter-epi dielectric thickness
US-2026096199-A1 · Apr 2, 2026 · US
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Strane Jay William patents
Strane Jay William is listed as an inventor on 55 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Strane Jay William |
| Total patents | 55 |
| First publication | Jul 15, 2021 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Placeholder profile formation for backside contact
US-12568669-B2 · Mar 3, 2026 · US
Stacked FET with bottom epi size control and wraparound backside contact
US-12557627-B2 · Feb 17, 2026 · US
Top contact structures for stacked transistors
US-12550420-B2 · Feb 10, 2026 · US
Monolithic stacked complementary transistor structures with dual work function metal gates
US-2026040675-A1 · Feb 5, 2026 · US
Monolithic stacked complementary transistor structures with dual work function metal gates
US-2026040674-A1 · Feb 5, 2026 · US
Self-aligned bottom spacer
US-12538565-B2 · Jan 27, 2026 · US
Shaped epitaxy
US-2025380452-A1 · Dec 11, 2025 · US
Dielectric inner spacers for nanosheet transistors
US-2025359322-A1 · Nov 20, 2025 · US
Asymmetric gate extension in stacked FET
US-12446290-B2 · Oct 14, 2025 · US
Recent patents
Latest publications not already listed above.
Stacked transistor frontside contact formation
US-2025248114-A1 · Jul 31, 2025 · US
Stacked field effect transistor with epitaxy cut for source/drain contact
US-2025239521-A1 · Jul 24, 2025 · US
Late gate extension
US-12356711-B2 · Jul 8, 2025 · US
Semiconductor device with stacked device types
US-2025203946-A1 · Jun 19, 2025 · US
Lateral passive diodes co-integrated with nanosheet technology
US-2025194242-A1 · Jun 12, 2025 · US
U-shaped spacer to protect the intra-device space region for stacked fet
US-2025185298-A1 · Jun 5, 2025 · US
Co-integration of passive device and vertically stacked nanosheets
US-2025185377-A1 · Jun 5, 2025 · US
Stacked field-effect transistor device with backside cut for top source/drain access
US-2025167118-A1 · May 22, 2025 · US
CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor
US-12310090-B2 · May 20, 2025 · US
Enlarged bottom contact area in stacked transistors
US-2025159997-A1 · May 15, 2025 · US
Field-effect transistor crescent-shaped dielectric isolation
US-2025113560-A1 · Apr 3, 2025 · US
Self-aligned C-shaped vertical field effect transistor
US-12268030-B2 · Apr 1, 2025 · US
Dual sided circuit connections
US-2025089336-A1 · Mar 13, 2025 · US
Stacked fet with bottom epi size control and wraparound backside contact
US-2025062190-A1 · Feb 20, 2025 · US
Local trapped metal contact for stacked fet
US-2025063795-A1 · Feb 20, 2025 · US
Shared source/drain contact for stacked transistors
US-2025040199-A1 · Jan 30, 2025 · US
Stacked fet with low parasitic-capacitance gate
US-2025006786-A1 · Jan 2, 2025 · US
Stacked field-effect transistors
US-12183740-B2 · Dec 31, 2024 · US
Merged self-aligned backside contact
US-2024429098-A1 · Dec 26, 2024 · US
Placeholder profile formation for backside contact
US-2024379769-A1 · Nov 14, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 55 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 44 |
| H10D30/6735 | 33 |
| H10D62/121 | 32 |
| H10D30/43 | 31 |
| H10D30/014 | 31 |