Fabrication of a vertical transistor with self-aligned bottom source/drain

Patent metadata

Field	Value
Publication number	US-10083871-B2
Application number	US-201615177358-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Jun 9, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.

First claim

What is claimed is:

1. A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
forming a doped layer on a substrate;
forming one or more vertical fins on the doped layer;
forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness; and
forming at least one isolation trench through the doped layer by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from a sidewall of at least one of the one or more vertical fins by the thickness of the protective layer.

2. The method of claim 1 , wherein the lateral offset defines a periphery of a doped region formed from the doped layer for a bottom source/drain.

3. The method of claim 1 , wherein the protective layer is formed on the one or more vertical fins by atomic layer deposition (ALD), chemical vapor deposition (CVD) or a combination thereof.

4. The method of claim 1 , wherein the protective layer has a thickness in the range of about 5 nm to about 50 nm.

5. The method of claim 1 , wherein the one or more isolation trench(es) extends through the doped layer to form two or more doped layer regions, wherein at least one vertical fin is on a first region and at least one vertical fin is on a second region.

6. The method of claim 5 , further comprising forming a gate structure on at least one of the one or more vertical fins, and forming a contact gap through the gate structure to one of the two or more doped layer regions.

7. The method of claim 1 , further comprising filling the at least one isolation trench with a dielectric spacer, wherein the dielectric spacer physically separates two or more vertical fins into at least two vertical fin field effect transistors (vertical finFETs).

8. The method of claim 7 , wherein the dielectric spacer is silicon nitride.

9. The method of claim 1 , further comprising forming a top source/drain on at least one of the one or more vertical fins.

10. A method of forming a vertical tin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
forming a doped layer on a substrate;
forming a plurality of vertical fins on the doped layer, wherein there is a distance between at least two adjacent vertical fins forming an intervening space;
forming a protective layer on the plurality of vertical fins on, wherein the protective layer has a thickness equal to or greater than half the distance between the at least two adjacent vertical fins, such that the protective layer fills the intervening space; and
forming at least one isolation trench through the doped layer by removing at least a portion of the protective layer on the doped layer, wherein the protective layer filling the intervening space prevents formation of the at least one isolation trench in the intervening space.

11. The method of claim 10 , wherein the distance between the at least two adjacent vertical fins is in the range of about 10 nm to about 100 nm.

12. The method of claim 10 , wherein the protective layer has a thickness in the range of about 5 nm to about 50 nm, and the thickness of the protective layer defines a lateral offset of the isolation trench from the plurality of vertical fins.

13. A vertical fin field effect transistor (vertical finFET) having a self-aligned bottom source/drain, comprising;
one or more doped layer regions on a substrate;
one or more vertical fins formed on one of the one or more doped layer regions, wherein the one of the one or more doped layer regions forms a bottom source/drain for the one or more vertical fins;
one or more dielectric spacer(s) on the substrate, wherein at least one of the one or more dielectric spacers) is offset from at least one of the one or more vertical fins by a width, W 1 , that defines a boundary along a side of one of the one or more doped layer regions; and
a metal contact between the at least one of the one or more dielectric spacer(s) and the at least one of the one or more vertical fins, wherein the metal contact is on the one of the one or more doped layer regions and in electrical contact with the one of the one or more doped layer regions.

14. The vertical finFET of claim 13 , wherein the width, W 1 , is in the range of about 5 nm to about 50 nm.

15. The vertical finFET of claim 13 , wherein the one or more doped layer regions is silicon germanium (SiGe) doped with boron to form a p-type FET.

16. The vertical finFET of claim 13 , further comprising a top source/drain on the one or more vertical fins formed on the one of the one or more doped layer regions, wherein the top source/drain is silicon germanium (SiGe) doped with boron to form a p-type FET.

17. The vertical finFET of claim 13 , wherein the one or more dielectric spacer(s) is silicon nitride (SiN).

18. The vertical finFET of claim 13 , wherein the metal contact is tungsten (W), copper (Cu), molybdenum (Mo), cobalt (Co), or a combination thereof.

19. The vertical finFET of claim 13 , further comprising a gate structure on the one or more vertical tins formed on the one of the one or more doped layer regions.

20. The vertical finFET of claim 19 , further comprising a gap line wherein the gap liner is between the gate structure and the at least one of the one or more dielectric spacer(s) offset from the at least one of the one or more vertical fins, and the gap liner physically and electrically separates the metal contact from the gate structure.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title