Uniform vertical field effect transistor spacers

Patent metadata

Field	Value
Publication number	US-10043874-B2
Application number	US-201715817325-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Jun 17, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls, a source area in contact with the vertical fin structure, a drain area in contact with the vertical fin structure, a plurality of spacers comprising a first oxide layer in contact with the source area, and a second oxide layer in contact with the drain area. The first oxide layer can have a thickness that is equal to a thickness of the second oxide layer.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a film stack on a substrate, the film stack comprising a bottom layer, a silicon layer on top of the bottom layer, and a top layer on top of the silicon layer;
patterning a plurality of vertical structures formed of the top layer and silicon layer;
selectively wet etching the silicon layer to form a plurality of vertical fins, the vertical fins having vertical sidewalls; and
simultaneously forming an oxide layer on the bottom layer and the top layer to create a plurality of spacers.

2. The method of claim 1 , wherein the bottom layer comprises SiGe.

3. The method of claim 1 , wherein the top layer comprises SiGe.

4. The method of claim 1 , wherein simultaneously forming an oxide layer on the top layer and the bottom layer to create a plurality of spacers comprises forming a plurality of oxide layers on the vertical sidewalls, a first oxide layer in contact with the top layer, and a second oxide layer in contact with the bottom layer.

5. The method of claim 2 further comprising removing the oxide layers on the vertical side walls.

6. The method of claim 1 , wherein the plurality of spacers have a uniform thickness.

7. The method of claim 1 , wherein simultaneously forming an oxide layer on the top layer and the bottom layer comprises oxidizing the semiconductor structure at a temperature of 600° C. to 750° C.

8. The method of claim 1 , wherein patterning the plurality of vertical structures comprises performing a sidewall image transfer.

9. The method of claim 1 , further comprising forming a plurality of gates around the plurality of vertical fins.

10. The method of claim 1 , wherein the plurality of spacers comprises a top spacer formed on the top layer and a bottom spacer formed on the bottom film layer.

11. The method of claim 10 , wherein the top spacer and the bottom spacer each has a thickness of less than 10 nm.

12. A method of forming a vertical semiconductor structure comprising:
depositing a first layer on a substrate, the first layer comprising a film composed of a material suitable for a source material or a drain material and having an oxidation rate that is faster than the oxidation rate for a silicon material;
depositing the silicon material on the first layer;
depositing a second layer of the film on the silicon material;
etching the semiconductor structure to form a vertical fin, a source, and a drain, wherein the source and drain are composed of the material and the vertical fin is composed of the silicon material; and
performing a low temperature oxidation on the semiconductor structure to create spacers around the source and the drain.

13. The method of claim 12 , wherein the spacers are created simultaneously.

14. The method of claim 12 further comprising forming a gate in between the source and the drain.

15. The method of claim 12 , wherein the first layer comprises SiGe.

16. The method of claim 12 , wherein the second layer comprises SiGe.

17. The method of claim 12 further comprising forming oxide layers on the vertical fins, on the source, and on the drain.

18. The method of claim 12 further comprising forming a gate around the vertical fin.

19. The method of claim 12 , wherein the spacers have a thickness of less than 10 nm.

20. The method of claim 12 , wherein the low temperature oxidation comprises oxidizing the semiconductor structure at a temperature of 600° C. to 750° C.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10D30/6219 Primary

  characterised by the source or drain electrodes · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L21/30604

  Electricity · mapped topic