Bottom spacer formation for vertical transistor

Patent metadata

Field	Value
Publication number	US-9954103-B1
Application number	US-201715714271-A
Country	US
Kind code	B1
Filing date	Sep 25, 2017
Priority date	Oct 26, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.

First claim

What is claimed is:

1. A semiconductor structure comprising:
at least one semiconductor fin extending upward from a surface of a substrate;
a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin;
a bottom spacer structure located on each bottom source/drain region, each bottom spacer structure comprising a silicon dioxide spacer and a silicon nitride spacer, wherein the silicon nitride spacer is entirely separated from the at least one semiconductor fin by a first portion of the silicon dioxide spacer and entirely separated from the bottom source/drain region by a second portion of the silicon dioxide spacer;
a functional gate structure located on each side of the at least one semiconductor fin and above the bottom spacer structure;
a top spacer located on each functional gate structure and contacting a sidewall of a portion of the at least one semiconductor fin; and
a top source/drain structure extending from each sidewall of an upper portion of the at least one semiconductor fin.

2. The semiconductor structure of claim 1 , wherein a topmost surface of each silicon nitride spacer is coplanar with a topmost surface of each silicon nitride spacer.

3. The semiconductor structure of claim 2 , wherein a portion of each functional gate structure directly contacts the topmost surface of the silicon dioxide spacer and the topmost surface of the silicon nitride spacer.

4. The semiconductor structure of claim 2 , wherein a bottommost surface of each silicon dioxide spacer is located directly on a topmost surface of the bottom source/drain region.

5. The semiconductor structure of claim 2 , wherein a bottommost surface of the silicon nitride spacer is present on a surface of the silicon dioxide spacer.

6. The semiconductor structure of claim 1 , wherein said substrate comprises a remaining portion of a bulk semiconductor substrate.

7. The semiconductor structure of claim 1 , wherein the at least one semiconductor fin and the substrate comprise a same semiconductor material.

8. The semiconductor structure of claim 1 , wherein each top source/drain structure has a faceted surface.

9. The semiconductor structure of claim 1 , wherein each top source/drain structure has a non-faceted surface.

10. The semiconductor structure of claim 1 , wherein each top source/drain structure is diamond shaped.

11. The semiconductor structure of claim 1 , wherein each top source/drain structure is triangularly shaped, and is present only on the sidewall of the at least one semiconductor fin.

12. The semiconductor structure of claim 1 , wherein each functional gate structure comprises a U-shaped gate dielectric liner portion, a U-shaped gate conductor liner portion, and a gate conductor portion.

13. The semiconductor structure of claim 12 , wherein the U-shaped gate dielectric liner portion, the U-shaped gate conductor liner portion, and the gate conductor portion have topmost surfaces that are coplanar with each other.

14. The semiconductor structure of claim 1 , wherein the top spacer has a height that is less than a height of the at least one semiconductor fin.

15. The semiconductor structure of claim 1 , wherein the at least one semiconductor fin, the bottom source/drain structure and the top source/drain structure comprise a same semiconductor material.

16. The semiconductor structure of claim 1 , wherein the bottom source/drain region and the top source/drain structure have a dopant concentration from 2×10 20 atoms/cm 3 to 1×10 21 atoms/cm 3 .

17. The semiconductor structure of claim 1 , wherein each functional gate structure comprises a U-shaped gate dielectric liner portion, wherein a bottommost surface of the U-shaped gate dielectric liner portion is in direct physically contact with topmost surfaces of both the silicon dioxide spacer and the silicon nitride spacer of the bottom spacer structure.

18. The semiconductor structure of claim 1 , wherein the at least one semiconductor fin has a height from 20 nm to 200 nm, and a width from 2 nm to 30 nm.

19. The semiconductor structure of claim 1 , wherein the at least one semiconductor fin comprises a plurality of spaced apart semiconductor fins, and each semiconductor fin has a height from 20 nm to 200 nm, and a width from 2 nm to 30 nm.

20. The semiconductor structure of claim 19 , wherein a pitch between each adjacent semiconductor fin of the plurality of spaced apart semiconductor fins is from 20 nm to 100 nm.

Assignees

• IBM

Inventors

• Gluschenkov Oleg
• Mehta Sanjay C
• Mochizuki Shogo
• Reznicek Alexander

Classifications

• H01L29/6656

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title