Vertical field-effect transistor having a dielectric spacer between a gate electrode edge and a self-aligned source/drain contact

Patent metadata

Field	Value
Publication number	US-10211315-B2
Application number	US-201715654165-A
Country	US
Kind code	B2
Filing date	Jul 19, 2017
Priority date	Jul 19, 2017
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.

First claim

What is claimed is:

1. A structure for a vertical-transport field effect transistor, the structure comprising:
a first source/drain region including a contact landing area;
a dielectric layer over the contact landing area;
a first spacer layer on the first source/drain region;
a second spacer layer;
a semiconductor fin projecting from the first source/drain region;
a gate electrode coupled with the semiconductor fin, the gate electrode including a first section arranged laterally between the semiconductor fin and the contact landing area, and the first section of the gate electrode having a side edge that is recessed relative to the first spacer layer and to the second spacer layer, to define a cavity with the first spacer layer and the second spacer layer;
a contact arranged in a contacting relationship with the contact landing area; and
a dielectric spacer laterally arranged in the cavity between the side edge of the first section of the gate electrode and the contact,
wherein the dielectric spacer and the first section of the gate electrode are arranged in a vertical direction between the first spacer layer and the second spacer layer, the contact extends in the vertical direction through the dielectric layer, the dielectric layer is comprised of a first dielectric material, and the dielectric spacer is comprised of a second dielectric material that has a different etch selectivity than the first dielectric material.

2. The structure of claim 1 wherein the contact has a directly contacting relationship with the dielectric spacer.

3. The structure of claim 1 wherein the first dielectric material is silicon dioxide, and the second dielectric material is silicon nitride.

4. A structure for a vertical-transport field effect transistor, the structure comprising:
a first source/drain region including a contact landing area;
a second source/drain region;
a first spacer layer on the first source/drain region;
a second spacer layer;
a semiconductor fin projecting from the first source/drain region;
a gate electrode coupled with the semiconductor fin, the gate electrode including a first section arranged laterally between the semiconductor fin and the contact landing area, and the first section of the gate electrode having a side edge that is recessed relative to the first spacer layer and to the second spacer layer to define a cavity;
a contact arranged in a contacting relationship with the contact landing area; and
a dielectric spacer laterally arranged in the cavity between the side edge of the first section of the gate electrode and the contact,
wherein the dielectric spacer and the first section of the gate electrode are arranged in a vertical direction between the first spacer layer and the second spacer layer, the gate electrode includes a second section that is arranged between the semiconductor fin and the first section, a portion of the second spacer layer is arranged in the vertical direction between the first section of the gate electrode and the second source/drain region, and the second source/drain region extends laterally to overlap with the portion of the second spacer layer.

5. The structure of claim 4 wherein the contact has a directly contacting relationship with the dielectric spacer.

6. The structure of claim 4 further comprising:
a dielectric layer over the contact landing area,
wherein the contact extends in the vertical direction through the dielectric layer, the dielectric layer is comprised of a first dielectric material, and the dielectric spacer is comprised of a second dielectric material that has a different etch selectivity than the first dielectric material.

7. The structure of claim 6 wherein the first dielectric material is silicon dioxide, and the second dielectric material is silicon nitride.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Huang Haigou

Classifications

• H01L29/66666 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/66787

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title